Commit db34c5ff authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'usb-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB / PHY updates from Greg KH:
 "Here are the big set of USB and PHY driver patches for 5.7-rc1.

  Nothing huge here, some new PHY drivers, loads of USB gadget fixes and
  updates, xhci updates, usb-serial driver updates and new device ids,
  and other minor things. Full details in the shortlog.

  All have been in linux-next for a while with no reported issues"

* tag 'usb-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (239 commits)
  USB: cdc-acm: restore capability check order
  usb: cdns3: make signed 1 bit bitfields unsigned
  usb: gadget: fsl: remove unused variable 'driver_desc'
  usb: gadget: f_fs: Fix use after free issue as part of queue failure
  usb: typec: Correct the documentation for typec_cable_put()
  USB: serial: io_edgeport: fix slab-out-of-bounds read in edge_interrupt_callback
  USB: serial: option: add Wistron Neweb D19Q1
  USB: serial: option: add BroadMobi BM806U
  USB: serial: option: add support for ASKEY WWHC050
  usb: core: Add ACPI support for USB interface devices
  driver core: platform: Reimplement devm_platform_ioremap_resource
  usb: dwc2: convert to devm_platform_get_and_ioremap_resource
  usb: host: hisilicon: convert to devm_platform_get_and_ioremap_resource
  usb: host: xhci-plat: convert to devm_platform_get_and_ioremap_resource
  drivers: provide devm_platform_get_and_ioremap_resource()
  phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHY
  phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHY
  dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parameters
  phy: qcom-qusb2: Add generic QUSB2 V2 PHY support
  dt-bindings: phy: qcom,qusb2: Add compatibles for QUSB2 V2 phy and SC7180
  ...
parents 063d1942 62d65bdd
...@@ -20,13 +20,13 @@ Date: April 2017 ...@@ -20,13 +20,13 @@ Date: April 2017
Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Description: Description:
The supported power roles. This attribute can be used to request The supported power roles. This attribute can be used to request
power role swap on the port when the port supports USB Power power role swap on the port. Swapping is supported as
Delivery. Swapping is supported as synchronous operation, so synchronous operation, so write(2) to the attribute will not
write(2) to the attribute will not return until the operation return until the operation has finished. The attribute is
has finished. The attribute is notified about role changes so notified about role changes so that poll(2) on the attribute
that poll(2) on the attribute wakes up. Change on the role will wakes up. Change on the role will also generate uevent
also generate uevent KOBJ_CHANGE. The current role is show in KOBJ_CHANGE. The current role is show in brackets, for example
brackets, for example "[source] sink" when in source mode. "[source] sink" when in source mode.
Valid values: source, sink Valid values: source, sink
...@@ -108,6 +108,15 @@ Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com> ...@@ -108,6 +108,15 @@ Contact: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Description: Description:
Revision number of the supported USB Type-C specification. Revision number of the supported USB Type-C specification.
What: /sys/class/typec/<port>/orientation
Date: February 2020
Contact: Badhri Jagan Sridharan <badhri@google.com>
Description:
Indicates the active orientation of the Type-C connector.
Valid values:
- "normal": CC1 orientation
- "reverse": CC2 orientation
- "unknown": Orientation cannot be determined.
USB Type-C partner devices (eg. /sys/class/typec/port0-partner/) USB Type-C partner devices (eg. /sys/class/typec/port0-partner/)
......
...@@ -14,6 +14,7 @@ properties: ...@@ -14,6 +14,7 @@ properties:
compatible: compatible:
enum: enum:
- amlogic,meson-g12a-usb2-phy - amlogic,meson-g12a-usb2-phy
- amlogic,meson-a1-usb2-phy
reg: reg:
maxItems: 1 maxItems: 1
...@@ -49,6 +50,19 @@ required: ...@@ -49,6 +50,19 @@ required:
- reset-names - reset-names
- "#phy-cells" - "#phy-cells"
if:
properties:
compatible:
enum:
- amlogic,meson-a1-usb-ctrl
then:
properties:
power-domains:
maxItems: 1
required:
- power-domains
examples: examples:
- | - |
phy@36000 { phy@36000 {
......
Cadence MHDP DisplayPort SD0801 PHY binding
===========================================
This binding describes the Cadence SD0801 PHY hardware included with
the Cadence MHDP DisplayPort controller.
-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible : Should be "cdns,dp-phy"
- reg : Defines the following sets of registers in the parent
mhdp device:
- Offset of the DPTX PHY configuration registers
- Offset of the SD0801 PHY configuration registers
- #phy-cells : from the generic PHY bindings, must be 0.
Optional properties:
- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
2430, 2700, 3240, 4320, 5400 or 8100)
-------------------------------------------------------------------------------
Example:
dp_phy: phy@f0fb030a00 {
compatible = "cdns,dp-phy";
reg = <0xf0 0xfb030a00 0x0 0x00000040>,
<0xf0 0xfb500000 0x0 0x00100000>;
num_lanes = <4>;
max_bit_rate = <8100>;
#phy-cells = <0>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Cadence Torrent SD0801 PHY binding for DisplayPort
description:
This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
hardware included with the Cadence MHDP DisplayPort controller.
maintainers:
- Swapnil Jakhade <sjakhade@cadence.com>
- Yuti Amonkar <yamonkar@cadence.com>
properties:
compatible:
enum:
- cdns,torrent-phy
- ti,j721e-serdes-10g
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
maxItems: 1
description:
PHY reference clock. Must contain an entry in clock-names.
clock-names:
const: refclk
reg:
minItems: 1
maxItems: 2
items:
- description: Offset of the Torrent PHY configuration registers.
- description: Offset of the DPTX PHY configuration registers.
reg-names:
minItems: 1
maxItems: 2
items:
- const: torrent_phy
- const: dptx_phy
resets:
maxItems: 1
description:
Torrent PHY reset.
See Documentation/devicetree/bindings/reset/reset.txt
patternProperties:
'^phy@[0-7]+$':
type: object
description:
Each group of PHY lanes with a single master lane should be represented as a sub-node.
properties:
reg:
description:
The master lane number. This is the lowest numbered lane in the lane group.
resets:
minItems: 1
maxItems: 4
description:
Contains list of resets, one per lane, to get all the link lanes out of reset.
"#phy-cells":
const: 0
cdns,phy-type:
description:
Specifies the type of PHY for which the group of PHY lanes is used.
Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 3, 4, 5, 6]
cdns,num-lanes:
description:
Number of DisplayPort lanes.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4]
default: 4
cdns,max-bit-rate:
description:
Maximum DisplayPort link bit rate to use, in Mbps
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
default: 8100
required:
- reg
- resets
- "#phy-cells"
- cdns,phy-type
additionalProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- reg
- reg-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/phy/phy.h>
torrent_phy: torrent-phy@f0fb500000 {
compatible = "cdns,torrent-phy";
reg = <0xf0 0xfb500000 0x0 0x00100000>,
<0xf0 0xfb030a00 0x0 0x00000040>;
reg-names = "torrent_phy", "dptx_phy";
resets = <&phyrst 0>;
clocks = <&ref_clk>;
clock-names = "refclk";
#address-cells = <1>;
#size-cells = <0>;
torrent_phy_dp: phy@0 {
reg = <0>;
resets = <&phyrst 1>, <&phyrst 2>,
<&phyrst 3>, <&phyrst 4>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <4>;
cdns,max-bit-rate = <8100>;
};
};
...
...@@ -13,10 +13,16 @@ Required properties (controller (parent) node): ...@@ -13,10 +13,16 @@ Required properties (controller (parent) node):
"mediatek,mt8173-u3phy"; "mediatek,mt8173-u3phy";
make use of "mediatek,generic-tphy-v1" on mt2701 instead and make use of "mediatek,generic-tphy-v1" on mt2701 instead and
"mediatek,generic-tphy-v2" on mt2712 instead. "mediatek,generic-tphy-v2" on mt2712 instead.
- clocks : (deprecated, use port's clocks instead) a list of phandle +
clock-specifier pairs, one for each entry in clock-names - #address-cells: the number of cells used to represent physical
- clock-names : (deprecated, use port's one instead) must contain base addresses.
"u3phya_ref": for reference clock of usb3.0 analog phy. - #size-cells: the number of cells used to represent the size of an address.
- ranges: the address mapping relationship to the parent, defined with
- empty value: if optional 'reg' is used.
- non-empty value: if optional 'reg' is not used. should set
the child's base address to 0, the physical address
within parent's address space, and the length of
the address map.
Required nodes : a sub-node is required for each port the controller Required nodes : a sub-node is required for each port the controller
provides. Address range information including the usual provides. Address range information including the usual
...@@ -34,12 +40,6 @@ Optional properties (controller (parent) node): ...@@ -34,12 +40,6 @@ Optional properties (controller (parent) node):
Required properties (port (child) node): Required properties (port (child) node):
- reg : address and length of the register set for the port. - reg : address and length of the register set for the port.
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names : must contain
"ref": 48M reference clock for HighSpeed analog phy; and 26M
reference clock for SuperSpeed analog phy, sometimes is
24M, 25M or 27M, depended on platform.
- #phy-cells : should be 1 (See second example) - #phy-cells : should be 1 (See second example)
cell after port phandle is phy type from: cell after port phandle is phy type from:
- PHY_TYPE_USB2 - PHY_TYPE_USB2
...@@ -48,10 +48,22 @@ Required properties (port (child) node): ...@@ -48,10 +48,22 @@ Required properties (port (child) node):
- PHY_TYPE_SATA - PHY_TYPE_SATA
Optional properties (PHY_TYPE_USB2 port (child) node): Optional properties (PHY_TYPE_USB2 port (child) node):
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock-names
- clock-names : may contain
"ref": 48M reference clock for HighSpeed (digital) phy; and 26M
reference clock for SuperSpeed (digital) phy, sometimes is
24M, 25M or 27M, depended on platform.
"da_ref": the reference clock of analog phy, used if the clocks
of analog and digital phys are separated, otherwise uses
"ref" clock only if needed.
- mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-src : u32, the value of slew rate calibrate
- mediatek,eye-vrt : u32, the selection of VRT reference voltage - mediatek,eye-vrt : u32, the selection of VRT reference voltage
- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
- mediatek,bc12 : bool, enable BC12 of u2phy if support it - mediatek,bc12 : bool, enable BC12 of u2phy if support it
- mediatek,discth : u32, the selection of disconnect threshold
- mediatek,intr : u32, the selection of internal R (resistance)
Example: Example:
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm QUSB2 phy controller
maintainers:
- Manu Gautam <mgautam@codeaurora.org>
description:
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- items:
- enum:
- qcom,sc7180-qusb2-phy
- qcom,sdm845-qusb2-phy
- const: qcom,qusb2-v2-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
minItems: 2
maxItems: 3
items:
- description: phy config clock
- description: 19.2 MHz ref clk
- description: phy interface clock (Optional)
clock-names:
minItems: 2
maxItems: 3
items:
- const: cfg_ahb
- const: ref
- const: iface
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
vdda-phy-dpdm-supply:
description:
Phandle to 3.1V regulator supply to Dp/Dm port signals.
resets:
maxItems: 1
description:
Phandle to reset to phy block.
nvmem-cells:
maxItems: 1
description:
Phandle to nvmem cell that contains 'HS Tx trim'
tuning parameter value for qusb2 phy.
qcom,tcsr-syscon:
description:
Phandle to TCSR syscon register region.
$ref: /schemas/types.yaml#/definitions/phandle
if:
properties:
compatible:
contains:
const: qcom,qusb2-v2-phy
then:
properties:
qcom,imp-res-offset-value:
description:
It is a 6 bit value that specifies offset to be
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
tuning parameter that may vary for different boards of same SOC.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 63
default: 0
qcom,bias-ctrl-value:
description:
It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
tuning parameter that may vary for different boards of same SOC.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 63
default: 0
qcom,charge-ctrl-value:
description:
It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
tuning parameter that may vary for different boards of same SOC.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 3
default: 0
qcom,hstx-trim-value:
description:
It is a 4 bit value that specifies tuning for HSTX
output current.
Possible range is - 15mA to 24mA (stepsize of 600 uA).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 15
default: 3
qcom,preemphasis-level:
description:
It is a 2 bit value that specifies pre-emphasis level.
Possible range is 0 to 15% (stepsize of 5%).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 3
default: 2
qcom,preemphasis-width:
description:
It is a 1 bit value that specifies how long the HSTX
pre-emphasis (specified using qcom,preemphasis-level) must be in
effect. Duration could be half-bit of full-bit.
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 1
default: 0
qcom,hsdisc-trim-value:
description:
It is a 2 bit value tuning parameter that control disconnect
threshold and may vary for different boards of same SOC.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
maximum: 3
default: 0
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- vdda-pll-supply
- vdda-phy-dpdm-supply
- resets
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
hsusb_phy: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-dpdm-supply = <&pm8994_l24>;
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
maintainers:
- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
description: |
Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
properties:
compatible:
enum:
- qcom,usb-hs-28nm-femtophy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
items:
- description: rpmcc ref clock
- description: PHY AHB clock
- description: Rentention clock
clock-names:
items:
- const: ref
- const: ahb
- const: sleep
resets:
items:
- description: PHY core reset
- description: POR reset
reset-names:
items:
- const: phy
- const: por
vdd-supply:
description: phandle to the regulator VDD supply node.
vdda1p8-supply:
description: phandle to the regulator 1.8V supply node.
vdda3p3-supply:
description: phandle to the regulator 3.3V supply node.
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- resets
- reset-names
- vdd-supply
- vdda1p8-supply
- vdda3p3-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
usb2_phy_prim: phy@7a000 {
compatible = "qcom,usb-hs-28nm-femtophy";
reg = <0x0007a000 0x200>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ref", "ahb", "sleep";
resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
<&gcc GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
vdd-supply = <&vreg_l4_1p2>;
vdda1p8-supply = <&vreg_l5_1p8>;
vdda3p3-supply = <&vreg_l12_3p3>;
};
...
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
maintainers:
- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
description: |
Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
properties:
compatible:
enum:
- qcom,usb-ss-28nm-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
items:
- description: rpmcc clock
- description: PHY AHB clock
- description: SuperSpeed pipe clock
clock-names:
items:
- const: ref
- const: ahb
- const: pipe
vdd-supply:
description: phandle to the regulator VDD supply node.
vdda1p8-supply:
description: phandle to the regulator 1.8V supply node.
resets:
items:
- description: COM reset
- description: PHY reset line
reset-names:
items:
- const: com
- const: phy
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- vdd-supply
- vdda1p8-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
usb3_phy: usb3-phy@78000 {
compatible = "qcom,usb-ss-28nm-phy";
reg = <0x78000 0x400>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ref", "ahb", "pipe";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
vdd-supply = <&vreg_l3_1p05>;
vdda1p8-supply = <&vreg_l5_1p8>;
};
...
Qualcomm DWC3 HS AND SS PHY CONTROLLER
--------------------------------------
DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
controllers. Each DWC3 PHY controller should have its own node.
Required properties:
- compatible: should contain one of the following:
- "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
- "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
- reg: offset and length of the DWC3 PHY controller register set
- #phy-cells: must be zero
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
clock-names.
- clock-names: Should contain "ref" for the PHY reference clock
Optional clocks:
"xo" External reference clock
Example:
phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
...@@ -8,10 +8,13 @@ Required properties: ...@@ -8,10 +8,13 @@ Required properties:
- compatible: compatible list, contains: - compatible: compatible list, contains:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
"qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
"qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998, "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
"qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
"qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845, "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
...@@ -44,6 +47,8 @@ Required properties: ...@@ -44,6 +47,8 @@ Required properties:
For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed. For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
For "qcom,msm8996-qmp-pcie-phy" must contain: For "qcom,msm8996-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref". "aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-ufs-phy" must contain:
"ref".
For "qcom,msm8996-qmp-usb3-phy" must contain: For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref". "aux", "cfg_ahb", "ref".
For "qcom,msm8998-qmp-usb3-phy" must contain: For "qcom,msm8998-qmp-usb3-phy" must contain:
...@@ -52,6 +57,10 @@ Required properties: ...@@ -52,6 +57,10 @@ Required properties:
"ref", "ref_aux". "ref", "ref_aux".
For "qcom,msm8998-qmp-pcie-phy" must contain: For "qcom,msm8998-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref". "aux", "cfg_ahb", "ref".
For "qcom,sdm845-qhp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref", "refgen".
For "qcom,sdm845-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref", "refgen".
For "qcom,sdm845-qmp-usb3-phy" must contain: For "qcom,sdm845-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref", "com_aux". "aux", "cfg_ahb", "ref", "com_aux".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain: For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
...@@ -72,6 +81,8 @@ Required properties: ...@@ -72,6 +81,8 @@ Required properties:
"phy", "common". "phy", "common".
For "qcom,msm8996-qmp-pcie-phy" must contain: For "qcom,msm8996-qmp-pcie-phy" must contain:
"phy", "common", "cfg". "phy", "common", "cfg".
For "qcom,msm8996-qmp-ufs-phy": must contain:
"ufsphy".
For "qcom,msm8996-qmp-usb3-phy" must contain For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common". "phy", "common".
For "qcom,msm8998-qmp-usb3-phy" must contain For "qcom,msm8998-qmp-usb3-phy" must contain
...@@ -80,6 +91,10 @@ Required properties: ...@@ -80,6 +91,10 @@ Required properties:
"ufsphy". "ufsphy".
For "qcom,msm8998-qmp-pcie-phy" must contain: For "qcom,msm8998-qmp-pcie-phy" must contain:
"phy", "common". "phy", "common".
For "qcom,sdm845-qhp-pcie-phy" must contain:
"phy".
For "qcom,sdm845-qmp-pcie-phy" must contain:
"phy".
For "qcom,sdm845-qmp-usb3-phy" must contain: For "qcom,sdm845-qmp-usb3-phy" must contain:
"phy", "common". "phy", "common".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain: For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
......
Qualcomm QUSB2 phy controller
=============================
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
"qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
- clocks: a list of phandles and clock-specifier pairs,
one for each entry in clock-names.
- clock-names: must be "cfg_ahb" for phy config clock,
"ref" for 19.2 MHz ref clk,
"iface" for phy interface clock (Optional).
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
- vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
- resets: Phandle to reset to phy block.
Optional properties:
- nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
tuning parameter value for qusb2 phy.
- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
- qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
tuning parameter that may vary for different boards of same SOC.
This property is applicable to only QUSB2 v2 PHY (sdm845).
- qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
output current.
Possible range is - 15mA to 24mA (stepsize of 600 uA).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is 22.2mA for sdm845.
- qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
Possible range is 0 to 15% (stepsize of 5%).
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is 10% for sdm845.
- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
pre-emphasis (specified using qcom,preemphasis-level) must be in
effect. Duration could be half-bit of full-bit.
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
This property is applicable to only QUSB2 v2 PHY (sdm845).
Default value is full-bit width for sdm845.
Example:
hsusb_phy: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>,
clock-names = "cfg_ahb", "ref";
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-dpdm-supply = <&pm8994_l24>;
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
};
...@@ -40,6 +40,7 @@ Required properties: ...@@ -40,6 +40,7 @@ Required properties:
"ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
"ti,am43xx-phy-gmii-sel" for am43xx platform "ti,am43xx-phy-gmii-sel" for am43xx platform
"ti,dm814-phy-gmii-sel" for dm814x platform "ti,dm814-phy-gmii-sel" for dm814x platform
"ti,am654-phy-gmii-sel" for AM654x/J721E platform
- reg : Address and length of the register set for the device - reg : Address and length of the register set for the device
- #phy-cells : must be 2. - #phy-cells : must be 2.
cell 1 - CPSW port number (starting from 1) cell 1 - CPSW port number (starting from 1)
......
...@@ -5,14 +5,19 @@ PCIe controller implemented on Socionext UniPhier SoCs. ...@@ -5,14 +5,19 @@ PCIe controller implemented on Socionext UniPhier SoCs.
Required properties: Required properties:
- compatible: Should contain one of the following: - compatible: Should contain one of the following:
"socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY
"socionext,uniphier-ld20-pcie-phy" - for LD20 PHY "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
"socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
- reg: Specifies offset and length of the register set for the device. - reg: Specifies offset and length of the register set for the device.
- #phy-cells: Must be zero. - #phy-cells: Must be zero.
- clocks: A phandle to the clock gate for PCIe glue layer including - clocks: A list of phandles to the clock gate for PCIe glue layer
this phy. including this phy.
- resets: A phandle to the reset line for PCIe glue layer including - clock-names: For Pro5 only, should contain the following:
this phy. "gio", "link" - for Pro5 SoC
- resets: A list of phandles to the reset line for PCIe glue layer
including this phy.
- reset-names: For Pro5 only, should contain the following:
"gio", "link" - for Pro5 SoC
Optional properties: Optional properties:
- socionext,syscon: A phandle to system control to set configurations - socionext,syscon: A phandle to system control to set configurations
......
...@@ -7,7 +7,7 @@ this describes about High-Speed PHY. ...@@ -7,7 +7,7 @@ this describes about High-Speed PHY.
Required properties: Required properties:
- compatible: Should contain one of the following: - compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC "socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC
"socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
...@@ -16,13 +16,13 @@ Required properties: ...@@ -16,13 +16,13 @@ Required properties:
- clocks: A list of phandles to the clock gate for USB3 glue layer. - clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required. According to the clock-names, appropriate clocks are required.
- clock-names: Should contain the following: - clock-names: Should contain the following:
"gio", "link" - for Pro4 SoC "gio", "link" - for Pro5 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others "phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer. - resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required. According to the reset-names, appropriate resets are required.
- reset-names: Should contain the following: - reset-names: Should contain the following:
"gio", "link" - for Pro4 SoC "gio", "link" - for Pro5 SoC
"phy", "link" - for others "phy", "link" - for others
Optional properties: Optional properties:
......
...@@ -8,6 +8,7 @@ this describes about Super-Speed PHY. ...@@ -8,6 +8,7 @@ this describes about Super-Speed PHY.
Required properties: Required properties:
- compatible: Should contain one of the following: - compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
"socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC
"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
...@@ -16,13 +17,13 @@ Required properties: ...@@ -16,13 +17,13 @@ Required properties:
- clocks: A list of phandles to the clock gate for USB3 glue layer. - clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required. According to the clock-names, appropriate clocks are required.
- clock-names: - clock-names:
"gio", "link" - for Pro4 SoC "gio", "link" - for Pro4 and Pro5 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others "phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer. - resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required. According to the reset-names, appropriate resets are required.
- reset-names: - reset-names:
"gio", "link" - for Pro4 SoC "gio", "link" - for Pro4 and Pro5 SoC
"phy", "link" - for others "phy", "link" - for others
Optional properties: Optional properties:
......
...@@ -22,10 +22,14 @@ description: | ...@@ -22,10 +22,14 @@ description: |
The DWC3 Glue controls the PHY routing and power, an interrupt line is The DWC3 Glue controls the PHY routing and power, an interrupt line is
connected to the Glue to serve as OTG ID change detection. connected to the Glue to serve as OTG ID change detection.
The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
host-only mode.
properties: properties:
compatible: compatible:
enum: enum:
- amlogic,meson-g12a-usb-ctrl - amlogic,meson-g12a-usb-ctrl
- amlogic,meson-a1-usb-ctrl
ranges: true ranges: true
...@@ -84,6 +88,25 @@ required: ...@@ -84,6 +88,25 @@ required:
- phys - phys
- dr_mode - dr_mode
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-a1-usb-ctrl
then:
properties:
clocks:
minItems: 3
clock-names:
items:
- const: usb_ctrl
- const: usb_bus
- const: xtal_usb_ctrl
required:
- clock-names
examples: examples:
- | - |
usb: usb@ffe09000 { usb: usb@ffe09000 {
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 Facebook Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/aspeed,usb-vhub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED USB 2.0 Virtual Hub Controller
maintainers:
- Benjamin Herrenschmidt <benh@kernel.crashing.org>
description: |+
The ASPEED USB 2.0 Virtual Hub Controller implements 1 set of USB Hub
register and several sets of Device and Endpoint registers to support
the Virtual Hub's downstream USB devices.
Supported number of devices and endpoints vary depending on hardware
revisions. AST2400 and AST2500 Virtual Hub supports 5 downstream devices
and 15 generic endpoints, while AST2600 Virtual Hub supports 7 downstream
devices and 21 generic endpoints.
properties:
compatible:
enum:
- aspeed,ast2400-usb-vhub
- aspeed,ast2500-usb-vhub
- aspeed,ast2600-usb-vhub
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
aspeed,vhub-downstream-ports:
description: Number of downstream ports supported by the Virtual Hub
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 5
minimum: 1
maximum: 7
aspeed,vhub-generic-endpoints:
description: Number of generic endpoints supported by the Virtual Hub
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 15
minimum: 1
maximum: 21
required:
- compatible
- reg
- clocks
- interrupts
- aspeed,vhub-downstream-ports
- aspeed,vhub-generic-endpoints
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
vhub: usb-vhub@1e6a0000 {
compatible = "aspeed,ast2500-usb-vhub";
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <5>;
aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
};
...@@ -18,27 +18,15 @@ properties: ...@@ -18,27 +18,15 @@ properties:
- const: rockchip,rk3066-usb - const: rockchip,rk3066-usb
- const: snps,dwc2 - const: snps,dwc2
- items: - items:
- const: rockchip,px30-usb - enum:
- const: rockchip,rk3066-usb - rockchip,px30-usb
- const: snps,dwc2 - rockchip,rk3036-usb
- items: - rockchip,rk3188-usb
- const: rockchip,rk3036-usb - rockchip,rk3228-usb
- const: rockchip,rk3066-usb - rockchip,rk3288-usb
- const: snps,dwc2 - rockchip,rk3328-usb
- items: - rockchip,rk3368-usb
- const: rockchip,rv1108-usb - rockchip,rv1108-usb
- const: rockchip,rk3066-usb
- const: snps,dwc2
- items:
- const: rockchip,rk3188-usb
- const: rockchip,rk3066-usb
- const: snps,dwc2
- items:
- const: rockchip,rk3228-usb
- const: rockchip,rk3066-usb
- const: snps,dwc2
- items:
- const: rockchip,rk3288-usb
- const: rockchip,rk3066-usb - const: rockchip,rk3066-usb
- const: snps,dwc2 - const: snps,dwc2
- const: lantiq,arx100-usb - const: lantiq,arx100-usb
......
...@@ -7,7 +7,8 @@ Required properties: ...@@ -7,7 +7,8 @@ Required properties:
- compatible: must be "snps,dwc3" - compatible: must be "snps,dwc3"
- reg : Address and length of the register set for the device - reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller. - interrupts: Interrupts used by the dwc3 controller.
- clock-names: should contain "ref", "bus_early", "suspend" - clock-names: list of clock names. Ideally should be "ref",
"bus_early", "suspend" but may be less or more.
- clocks: list of phandle and clock specifier pairs corresponding to - clocks: list of phandle and clock specifier pairs corresponding to
entries in the clock-names property. entries in the clock-names property.
...@@ -36,7 +37,7 @@ Optional properties: ...@@ -36,7 +37,7 @@ Optional properties:
- phys: from the *Generic PHY* bindings - phys: from the *Generic PHY* bindings
- phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
or "usb3-phy". or "usb3-phy".
- resets: a single pair of phandle and reset specifier - resets: set of phandle and reset specifier pairs
- snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
- snps,usb3_lpm_capable: determines if platform is USB3 LPM capable - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
- snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command
...@@ -75,6 +76,8 @@ Optional properties: ...@@ -75,6 +76,8 @@ Optional properties:
from P0 to P1/P2/P3 without delay. from P0 to P1/P2/P3 without delay.
- snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
during HS transmit. during HS transmit.
- snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in
park mode are disabled.
- snps,dis_metastability_quirk: when set, disable metastability workaround. - snps,dis_metastability_quirk: when set, disable metastability workaround.
CAUTION: use only if you are absolutely sure of it. CAUTION: use only if you are absolutely sure of it.
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
......
...@@ -35,6 +35,12 @@ Optional properties: ...@@ -35,6 +35,12 @@ Optional properties:
the USB data role (USB host or USB device) for a given the USB data role (USB host or USB device) for a given
USB connector, such as Type-C, Type-B(micro). USB connector, such as Type-C, Type-B(micro).
see connector/usb-connector.txt. see connector/usb-connector.txt.
- role-switch-default-mode: indicating if usb-role-switch is enabled, the
device default operation mode of controller while usb
role is USB_ROLE_NONE. Valid arguments are "host" and
"peripheral". Defaults to "peripheral" if not
specified.
This is an attribute to a USB controller such as: This is an attribute to a USB controller such as:
......
Ingenic JZ4740 MUSB driver
Required properties:
- compatible: Must be "ingenic,jz4740-musb"
- reg: Address range of the UDC register set
- interrupts: IRQ number related to the UDC hardware
- interrupt-names: must be "mc"
- clocks: phandle to the "udc" clock
- clock-names: must be "udc"
- phys: phandle to the USB PHY
Example:
usb_phy: usb-phy@0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
udc: usb@13040000 {
compatible = "ingenic,jz4740-musb";
reg = <0x13040000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <24>;
interrupt-names = "mc";
clocks = <&cgu JZ4740_CLK_UDC>;
clock-names = "udc";
phys = <&usb_phy>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic JZ4770 USB PHY devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
$nodename:
pattern: '^usb-phy@.*'
compatible:
enum:
- ingenic,jz4770-phy
reg:
maxItems: 1
clocks:
maxItems: 1
vcc-supply:
description: VCC power supply
'#phy-cells':
const: 0
required:
- compatible
- reg
- clocks
- vcc-supply
- '#phy-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4770-cgu.h>
otg_phy: usb-phy@3c {
compatible = "ingenic,jz4770-phy";
reg = <0x3c 0x10>;
vcc-supply = <&vcc>;
clocks = <&cgu JZ4770_CLK_OTG_PHY>;
#phy-cells = <0>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ingenic,musb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic JZ47xx USB IP DT bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
$nodename:
pattern: '^usb@.*'
compatible:
oneOf:
- enum:
- ingenic,jz4770-musb
- ingenic,jz4740-musb
- items:
- const: ingenic,jz4725b-musb
- const: ingenic,jz4740-musb
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: udc
interrupts:
maxItems: 1
interrupt-names:
items:
- const: mc
phys:
description: PHY specifier for the USB PHY
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- phys
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4740-cgu.h>
usb_phy: usb-phy@0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
udc: usb@13040000 {
compatible = "ingenic,jz4740-musb";
reg = <0x13040000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <24>;
interrupt-names = "mc";
clocks = <&cgu JZ4740_CLK_UDC>;
clock-names = "udc";
phys = <&usb_phy>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/maxim,max3420-udc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MAXIM MAX3420/1 USB Peripheral Controller
maintainers:
- Jassi Brar <jaswinder.singh@linaro.org>
description: |
The controller provices USB2.0 compliant FullSpeed peripheral
implementation over the SPI interface.
Specifications about the part can be found at:
http://datasheets.maximintegrated.com/en/ds/MAX3420E.pdf
properties:
compatible:
enum:
- maxim,max3420-udc
- maxim,max3421-udc
reg:
maxItems: 1
interrupts:
items:
- description: usb irq from max3420
- description: vbus detection irq
minItems: 1
maxItems: 2
interrupt-names:
items:
- const: udc
- const: vbus
minItems: 1
maxItems: 2
spi-max-frequency:
maximum: 26000000
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi0 {
#address-cells = <1>;
#size-cells = <0>;
udc@0 {
compatible = "maxim,max3420-udc";
reg = <0>;
interrupt-parent = <&gpio>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "udc", "vbus";
spi-max-frequency = <12500000>;
};
};
...@@ -53,9 +53,7 @@ in need to reconfigure the pins on the connector, the alternate mode driver ...@@ -53,9 +53,7 @@ in need to reconfigure the pins on the connector, the alternate mode driver
needs to notify the bus using :c:func:`typec_altmode_notify()`. The driver needs to notify the bus using :c:func:`typec_altmode_notify()`. The driver
passes the negotiated SVID specific pin configuration value to the function as passes the negotiated SVID specific pin configuration value to the function as
parameter. The bus driver will then configure the mux behind the connector using parameter. The bus driver will then configure the mux behind the connector using
that value as the state value for the mux, and also call blocking notification that value as the state value for the mux.
chain to notify the external drivers about the state of the connector that need
to know it.
NOTE: The SVID specific pin configuration values must always start from NOTE: The SVID specific pin configuration values must always start from
``TYPEC_STATE_MODAL``. USB Type-C specification defines two default states for ``TYPEC_STATE_MODAL``. USB Type-C specification defines two default states for
...@@ -80,19 +78,6 @@ Helper macro ``TYPEC_MODAL_STATE()`` can also be used:: ...@@ -80,19 +78,6 @@ Helper macro ``TYPEC_MODAL_STATE()`` can also be used::
#define ALTMODEX_CONF_A = TYPEC_MODAL_STATE(0); #define ALTMODEX_CONF_A = TYPEC_MODAL_STATE(0);
#define ALTMODEX_CONF_B = TYPEC_MODAL_STATE(1); #define ALTMODEX_CONF_B = TYPEC_MODAL_STATE(1);
Notification chain
~~~~~~~~~~~~~~~~~~
The drivers for the components that the alternate modes are designed for need to
get details regarding the results of the negotiation with the partner, and the
pin configuration of the connector. In case of DisplayPort alternate mode for
example, the GPU drivers will need to know those details. In case of
Thunderbolt alternate mode, the thunderbolt drivers will need to know them, and
so on.
The notification chain is designed for this purpose. The drivers can register
notifiers with :c:func:`typec_altmode_register_notifier()`.
Cable plug alternate modes Cable plug alternate modes
~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~
...@@ -129,8 +114,3 @@ Cable Plug operations ...@@ -129,8 +114,3 @@ Cable Plug operations
.. kernel-doc:: drivers/usb/typec/bus.c .. kernel-doc:: drivers/usb/typec/bus.c
:functions: typec_altmode_get_plug typec_altmode_put_plug :functions: typec_altmode_get_plug typec_altmode_put_plug
Notifications
~~~~~~~~~~~~~
.. kernel-doc:: drivers/usb/typec/class.c
:functions: typec_altmode_register_notifier typec_altmode_unregister_notifier
...@@ -22,6 +22,7 @@ USB support ...@@ -22,6 +22,7 @@ USB support
misc_usbsevseg misc_usbsevseg
mtouchusb mtouchusb
ohci ohci
raw-gadget
usbip_protocol usbip_protocol
usbmon usbmon
usb-serial usb-serial
......
==============
USB Raw Gadget
==============
USB Raw Gadget is a kernel module that provides a userspace interface for
the USB Gadget subsystem. Essentially it allows to emulate USB devices
from userspace. Enabled with CONFIG_USB_RAW_GADGET. Raw Gadget is
currently a strictly debugging feature and shouldn't be used in
production, use GadgetFS instead.
Comparison to GadgetFS
~~~~~~~~~~~~~~~~~~~~~~
Raw Gadget is similar to GadgetFS, but provides a more low-level and
direct access to the USB Gadget layer for the userspace. The key
differences are:
1. Every USB request is passed to the userspace to get a response, while
GadgetFS responds to some USB requests internally based on the provided
descriptors. However note, that the UDC driver might respond to some
requests on its own and never forward them to the Gadget layer.
2. GadgetFS performs some sanity checks on the provided USB descriptors,
while Raw Gadget allows you to provide arbitrary data as responses to
USB requests.
3. Raw Gadget provides a way to select a UDC device/driver to bind to,
while GadgetFS currently binds to the first available UDC.
4. Raw Gadget uses predictable endpoint names (handles) across different
UDCs (as long as UDCs have enough endpoints of each required transfer
type).
5. Raw Gadget has ioctl-based interface instead of a filesystem-based one.
Userspace interface
~~~~~~~~~~~~~~~~~~~
To create a Raw Gadget instance open /dev/raw-gadget. Multiple raw-gadget
instances (bound to different UDCs) can be used at the same time. The
interaction with the opened file happens through the ioctl() calls, see
comments in include/uapi/linux/usb/raw_gadget.h for details.
The typical usage of Raw Gadget looks like:
1. Open Raw Gadget instance via /dev/raw-gadget.
2. Initialize the instance via USB_RAW_IOCTL_INIT.
3. Launch the instance with USB_RAW_IOCTL_RUN.
4. In a loop issue USB_RAW_IOCTL_EVENT_FETCH calls to receive events from
Raw Gadget and react to those depending on what kind of USB device
needs to be emulated.
Potential future improvements
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Implement ioctl's for setting/clearing halt status on endpoints.
- Reporting more events (suspend, resume, etc.) through
USB_RAW_IOCTL_EVENT_FETCH.
- Support O_NONBLOCK I/O.
...@@ -17218,6 +17218,12 @@ S: Maintained ...@@ -17218,6 +17218,12 @@ S: Maintained
F: Documentation/usb/acm.rst F: Documentation/usb/acm.rst
F: drivers/usb/class/cdc-acm.* F: drivers/usb/class/cdc-acm.*
USB APPLE MFI FASTCHARGE DRIVER
M: Bastien Nocera <hadess@hadess.net>
L: linux-usb@vger.kernel.org
S: Maintained
F: drivers/usb/misc/apple-mfi-fastcharge.c
USB AR5523 WIRELESS DRIVER USB AR5523 WIRELESS DRIVER
M: Pontus Fuchs <pontus.fuchs@gmail.com> M: Pontus Fuchs <pontus.fuchs@gmail.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
......
...@@ -164,6 +164,8 @@ vhub: usb-vhub@1e6a0000 { ...@@ -164,6 +164,8 @@ vhub: usb-vhub@1e6a0000 {
reg = <0x1e6a0000 0x300>; reg = <0x1e6a0000 0x300>;
interrupts = <5>; interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <5>;
aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2d_default>; pinctrl-0 = <&pinctrl_usb2d_default>;
status = "disabled"; status = "disabled";
......
...@@ -195,6 +195,8 @@ vhub: usb-vhub@1e6a0000 { ...@@ -195,6 +195,8 @@ vhub: usb-vhub@1e6a0000 {
reg = <0x1e6a0000 0x300>; reg = <0x1e6a0000 0x300>;
interrupts = <5>; interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <5>;
aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>; pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled"; status = "disabled";
......
...@@ -1112,6 +1112,31 @@ pinctrl_uart9_default: uart9_default { ...@@ -1112,6 +1112,31 @@ pinctrl_uart9_default: uart9_default {
groups = "UART9"; groups = "UART9";
}; };
pinctrl_usb2ah_default: usb2ah_default {
function = "USB2AH";
groups = "USBA";
};
pinctrl_usb2ad_default: usb2ad_default {
function = "USB2AD";
groups = "USBA";
};
pinctrl_usb2bh_default: usb2bh_default {
function = "USB2BH";
groups = "USBB";
};
pinctrl_usb2bd_default: usb2bd_default {
function = "USB2BD";
groups = "USBB";
};
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USBB";
};
pinctrl_vb_default: vb_default { pinctrl_vb_default: vb_default {
function = "VB"; function = "VB";
groups = "VB"; groups = "VB";
......
...@@ -245,6 +245,51 @@ mac3: ftgmac@1e690000 { ...@@ -245,6 +245,51 @@ mac3: ftgmac@1e690000 {
status = "disabled"; status = "disabled";
}; };
ehci0: usb@1e6a1000 {
compatible = "aspeed,ast2600-ehci", "generic-ehci";
reg = <0x1e6a1000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ah_default>;
status = "disabled";
};
ehci1: usb@1e6a3000 {
compatible = "aspeed,ast2600-ehci", "generic-ehci";
reg = <0x1e6a3000 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bh_default>;
status = "disabled";
};
uhci: usb@1e6b0000 {
compatible = "aspeed,ast2600-uhci", "generic-uhci";
reg = <0x1e6b0000 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#ports = <2>;
clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
status = "disabled";
/*
* No default pinmux, it will follow EHCI, use an
* explicit pinmux override if EHCI is not enabled.
*/
};
vhub: usb-vhub@1e6a0000 {
compatible = "aspeed,ast2600-usb-vhub";
reg = <0x1e6a0000 0x350>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled";
};
apb { apb {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
......
...@@ -62,6 +62,28 @@ struct resource *platform_get_resource(struct platform_device *dev, ...@@ -62,6 +62,28 @@ struct resource *platform_get_resource(struct platform_device *dev,
EXPORT_SYMBOL_GPL(platform_get_resource); EXPORT_SYMBOL_GPL(platform_get_resource);
#ifdef CONFIG_HAS_IOMEM #ifdef CONFIG_HAS_IOMEM
/**
* devm_platform_get_and_ioremap_resource - call devm_ioremap_resource() for a
* platform device and get resource
*
* @pdev: platform device to use both for memory resource lookup as well as
* resource management
* @index: resource index
* @res: optional output parameter to store a pointer to the obtained resource.
*/
void __iomem *
devm_platform_get_and_ioremap_resource(struct platform_device *pdev,
unsigned int index, struct resource **res)
{
struct resource *r;
r = platform_get_resource(pdev, IORESOURCE_MEM, index);
if (res)
*res = r;
return devm_ioremap_resource(&pdev->dev, r);
}
EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource);
/** /**
* devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
* device * device
...@@ -73,10 +95,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource); ...@@ -73,10 +95,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource);
void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
unsigned int index) unsigned int index)
{ {
struct resource *res; return devm_platform_get_and_ioremap_resource(pdev, index, NULL);
res = platform_get_resource(pdev, IORESOURCE_MEM, index);
return devm_ioremap_resource(&pdev->dev, res);
} }
EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
......
...@@ -66,7 +66,7 @@ ...@@ -66,7 +66,7 @@
#define PHY_CTRL_R14 0x38 #define PHY_CTRL_R14 0x38
#define PHY_CTRL_R14_I_RDP_EN BIT(0) #define PHY_CTRL_R14_I_RDP_EN BIT(0)
#define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1) #define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1)
#define PHY_CTRL_R14_I_RPU_SW2_EN GENMASK(2, 3) #define PHY_CTRL_R14_I_RPU_SW2_EN GENMASK(3, 2)
#define PHY_CTRL_R14_PG_RSTN BIT(4) #define PHY_CTRL_R14_PG_RSTN BIT(4)
#define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5) #define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5)
#define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6) #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6)
...@@ -146,11 +146,17 @@ ...@@ -146,11 +146,17 @@
#define RESET_COMPLETE_TIME 1000 #define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100 #define PLL_RESET_COMPLETE_TIME 100
enum meson_soc_id {
MESON_SOC_G12A = 0,
MESON_SOC_A1,
};
struct phy_meson_g12a_usb2_priv { struct phy_meson_g12a_usb2_priv {
struct device *dev; struct device *dev;
struct regmap *regmap; struct regmap *regmap;
struct clk *clk; struct clk *clk;
struct reset_control *reset; struct reset_control *reset;
int soc_id;
}; };
static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = { static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
...@@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) ...@@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
{ {
struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy); struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
int ret; int ret;
unsigned int value;
ret = reset_control_reset(priv->reset); ret = reset_control_reset(priv->reset);
if (ret) if (ret)
...@@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) ...@@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
regmap_write(priv->regmap, PHY_CTRL_R18, value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | PHY_CTRL_R18_MPLL_ACG_RANGE;
PHY_CTRL_R18_MPLL_ACG_RANGE);
if (priv->soc_id == MESON_SOC_A1)
value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
regmap_write(priv->regmap, PHY_CTRL_R18, value);
udelay(PLL_RESET_COMPLETE_TIME); udelay(PLL_RESET_COMPLETE_TIME);
...@@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) ...@@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) | FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0)); FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
regmap_write(priv->regmap, PHY_CTRL_R4, if (priv->soc_id == MESON_SOC_G12A)
FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | regmap_write(priv->regmap, PHY_CTRL_R4,
FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
PHY_CTRL_R4_TEST_BYPASS_MODE_EN | FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
else if (priv->soc_id == MESON_SOC_A1) {
regmap_write(priv->regmap, PHY_CTRL_R21,
PHY_CTRL_R21_USB2_CAL_ACK_EN |
PHY_CTRL_R21_USB2_TX_STRG_PD |
FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
/* Analog Settings */
regmap_write(priv->regmap, PHY_CTRL_R13,
FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
}
/* Tuning Disconnect Threshold */ /* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3, regmap_write(priv->regmap, PHY_CTRL_R3,
...@@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) ...@@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) | FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3)); FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
/* Analog Settings */ if (priv->soc_id == MESON_SOC_G12A) {
regmap_write(priv->regmap, PHY_CTRL_R14, 0); /* Analog Settings */
regmap_write(priv->regmap, PHY_CTRL_R13, regmap_write(priv->regmap, PHY_CTRL_R14, 0);
PHY_CTRL_R13_UPDATE_PMA_SIGNALS | regmap_write(priv->regmap, PHY_CTRL_R13,
FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
}
return 0; return 0;
} }
...@@ -286,6 +310,8 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) ...@@ -286,6 +310,8 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
if (IS_ERR(base)) if (IS_ERR(base))
return PTR_ERR(base); return PTR_ERR(base);
priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
priv->regmap = devm_regmap_init_mmio(dev, base, priv->regmap = devm_regmap_init_mmio(dev, base,
&phy_meson_g12a_usb2_regmap_conf); &phy_meson_g12a_usb2_regmap_conf);
if (IS_ERR(priv->regmap)) if (IS_ERR(priv->regmap))
...@@ -321,8 +347,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) ...@@ -321,8 +347,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
} }
static const struct of_device_id phy_meson_g12a_usb2_of_match[] = { static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
{ .compatible = "amlogic,g12a-usb2-phy", }, {
{ }, .compatible = "amlogic,g12a-usb2-phy",
.data = (void *)MESON_SOC_G12A,
},
{
.compatible = "amlogic,a1-usb2-phy",
.data = (void *)MESON_SOC_A1,
},
{ /* Sentinel */ }
}; };
MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match); MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
......
...@@ -3,13 +3,13 @@ ...@@ -3,13 +3,13 @@
# Phy drivers for Cadence PHYs # Phy drivers for Cadence PHYs
# #
config PHY_CADENCE_DP config PHY_CADENCE_TORRENT
tristate "Cadence MHDP DisplayPort PHY driver" tristate "Cadence Torrent PHY driver"
depends on OF depends on OF
depends on HAS_IOMEM depends on HAS_IOMEM
select GENERIC_PHY select GENERIC_PHY
help help
Support for Cadence MHDP DisplayPort PHY. Support for Cadence Torrent PHY.
config PHY_CADENCE_DPHY config PHY_CADENCE_DPHY
tristate "Cadence D-PHY Support" tristate "Cadence D-PHY Support"
......
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
This diff is collapsed.
This diff is collapsed.
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#define PA0_RG_USB20_INTR_EN BIT(5) #define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004 #define U3P_USBPHYACR1 0x004
#define PA1_RG_INTR_CAL GENMASK(23, 19)
#define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
#define PA1_RG_VRT_SEL GENMASK(14, 12) #define PA1_RG_VRT_SEL GENMASK(14, 12)
#define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12) #define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
#define PA1_RG_TERM_SEL GENMASK(10, 8) #define PA1_RG_TERM_SEL GENMASK(10, 8)
...@@ -60,6 +62,8 @@ ...@@ -60,6 +62,8 @@
#define U3P_USBPHYACR6 0x018 #define U3P_USBPHYACR6 0x018
#define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_DISCTH GENMASK(7, 4)
#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
#define PA6_RG_U2_SQTH GENMASK(3, 0) #define PA6_RG_U2_SQTH GENMASK(3, 0)
#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
...@@ -294,20 +298,21 @@ struct mtk_phy_instance { ...@@ -294,20 +298,21 @@ struct mtk_phy_instance {
struct u2phy_banks u2_banks; struct u2phy_banks u2_banks;
struct u3phy_banks u3_banks; struct u3phy_banks u3_banks;
}; };
struct clk *ref_clk; /* reference clock of anolog phy */ struct clk *ref_clk; /* reference clock of (digital) phy */
struct clk *da_ref_clk; /* reference clock of analog phy */
u32 index; u32 index;
u8 type; u8 type;
int eye_src; int eye_src;
int eye_vrt; int eye_vrt;
int eye_term; int eye_term;
int intr;
int discth;
bool bc12_en; bool bc12_en;
}; };
struct mtk_tphy { struct mtk_tphy {
struct device *dev; struct device *dev;
void __iomem *sif_base; /* only shared sif */ void __iomem *sif_base; /* only shared sif */
/* deprecated, use @ref_clk instead in phy instance */
struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
const struct mtk_phy_pdata *pdata; const struct mtk_phy_pdata *pdata;
struct mtk_phy_instance **phys; struct mtk_phy_instance **phys;
int nphys; int nphys;
...@@ -850,9 +855,14 @@ static void phy_parse_property(struct mtk_tphy *tphy, ...@@ -850,9 +855,14 @@ static void phy_parse_property(struct mtk_tphy *tphy,
&instance->eye_vrt); &instance->eye_vrt);
device_property_read_u32(dev, "mediatek,eye-term", device_property_read_u32(dev, "mediatek,eye-term",
&instance->eye_term); &instance->eye_term);
dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n", device_property_read_u32(dev, "mediatek,intr",
&instance->intr);
device_property_read_u32(dev, "mediatek,discth",
&instance->discth);
dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
instance->bc12_en, instance->eye_src, instance->bc12_en, instance->eye_src,
instance->eye_vrt, instance->eye_term); instance->eye_vrt, instance->eye_term,
instance->intr, instance->discth);
} }
static void u2_phy_props_set(struct mtk_tphy *tphy, static void u2_phy_props_set(struct mtk_tphy *tphy,
...@@ -888,6 +898,20 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, ...@@ -888,6 +898,20 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
writel(tmp, com + U3P_USBPHYACR1); writel(tmp, com + U3P_USBPHYACR1);
} }
if (instance->intr) {
tmp = readl(com + U3P_USBPHYACR1);
tmp &= ~PA1_RG_INTR_CAL;
tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
writel(tmp, com + U3P_USBPHYACR1);
}
if (instance->discth) {
tmp = readl(com + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_DISCTH;
tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
writel(tmp, com + U3P_USBPHYACR6);
}
} }
static int mtk_phy_init(struct phy *phy) static int mtk_phy_init(struct phy *phy)
...@@ -896,15 +920,16 @@ static int mtk_phy_init(struct phy *phy) ...@@ -896,15 +920,16 @@ static int mtk_phy_init(struct phy *phy)
struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
int ret; int ret;
ret = clk_prepare_enable(tphy->u3phya_ref); ret = clk_prepare_enable(instance->ref_clk);
if (ret) { if (ret) {
dev_err(tphy->dev, "failed to enable u3phya_ref\n"); dev_err(tphy->dev, "failed to enable ref_clk\n");
return ret; return ret;
} }
ret = clk_prepare_enable(instance->ref_clk); ret = clk_prepare_enable(instance->da_ref_clk);
if (ret) { if (ret) {
dev_err(tphy->dev, "failed to enable ref_clk\n"); dev_err(tphy->dev, "failed to enable da_ref\n");
clk_disable_unprepare(instance->ref_clk);
return ret; return ret;
} }
...@@ -967,7 +992,7 @@ static int mtk_phy_exit(struct phy *phy) ...@@ -967,7 +992,7 @@ static int mtk_phy_exit(struct phy *phy)
u2_phy_instance_exit(tphy, instance); u2_phy_instance_exit(tphy, instance);
clk_disable_unprepare(instance->ref_clk); clk_disable_unprepare(instance->ref_clk);
clk_disable_unprepare(tphy->u3phya_ref); clk_disable_unprepare(instance->da_ref_clk);
return 0; return 0;
} }
...@@ -1102,11 +1127,6 @@ static int mtk_tphy_probe(struct platform_device *pdev) ...@@ -1102,11 +1127,6 @@ static int mtk_tphy_probe(struct platform_device *pdev)
} }
} }
/* it's deprecated, make it optional for backward compatibility */
tphy->u3phya_ref = devm_clk_get_optional(dev, "u3phya_ref");
if (IS_ERR(tphy->u3phya_ref))
return PTR_ERR(tphy->u3phya_ref);
tphy->src_ref_clk = U3P_REF_CLK; tphy->src_ref_clk = U3P_REF_CLK;
tphy->src_coef = U3P_SLEW_RATE_COEF; tphy->src_coef = U3P_SLEW_RATE_COEF;
/* update parameters of slew rate calibrate if exist */ /* update parameters of slew rate calibrate if exist */
...@@ -1153,16 +1173,20 @@ static int mtk_tphy_probe(struct platform_device *pdev) ...@@ -1153,16 +1173,20 @@ static int mtk_tphy_probe(struct platform_device *pdev)
phy_set_drvdata(phy, instance); phy_set_drvdata(phy, instance);
port++; port++;
/* if deprecated clock is provided, ignore instance's one */ instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref");
if (tphy->u3phya_ref)
continue;
instance->ref_clk = devm_clk_get(&phy->dev, "ref");
if (IS_ERR(instance->ref_clk)) { if (IS_ERR(instance->ref_clk)) {
dev_err(dev, "failed to get ref_clk(id-%d)\n", port); dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
retval = PTR_ERR(instance->ref_clk); retval = PTR_ERR(instance->ref_clk);
goto put_child; goto put_child;
} }
instance->da_ref_clk =
devm_clk_get_optional(&phy->dev, "da_ref");
if (IS_ERR(instance->da_ref_clk)) {
dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port);
retval = PTR_ERR(instance->da_ref_clk);
goto put_child;
}
} }
provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
......
...@@ -91,3 +91,23 @@ config PHY_QCOM_USB_HSIC ...@@ -91,3 +91,23 @@ config PHY_QCOM_USB_HSIC
select GENERIC_PHY select GENERIC_PHY
help help
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on ARCH_QCOM || COMPILE_TEST
depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
select GENERIC_PHY
help
Enable this to support the Qualcomm Synopsys DesignWare Core 28nm
High-Speed PHY driver. This driver supports the Hi-Speed PHY which
is usually paired with either the ChipIdea or Synopsys DWC3 USB
IPs on MSM SOCs.
config PHY_QCOM_USB_SS
tristate "Qualcomm USB Super-Speed PHY driver"
depends on ARCH_QCOM || COMPILE_TEST
depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
select GENERIC_PHY
help
Enable this to support the Super-Speed USB transceiver on various
Qualcomm chipsets.
...@@ -10,3 +10,5 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o ...@@ -10,3 +10,5 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
This diff is collapsed.
...@@ -409,4 +409,118 @@ ...@@ -409,4 +409,118 @@
#define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8 #define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8
#define QPHY_V4_MULTI_LANE_CTRL1 0x1e0 #define QPHY_V4_MULTI_LANE_CTRL1 0x1e0
/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
/* PCIE GEN3 QHP Lane registers */
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
/* PCIE GEN3 PCS registers */
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
#endif #endif
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment