1. 10 Dec, 2004 10 commits
    • Tony Luck's avatar
      [IA64] hardirq.h: Add declaration for ack_bad_irq(). · 0734f5fc
      Tony Luck authored
      Cleanup a warning from my irq merge.
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      0734f5fc
    • Russ Anderson's avatar
      [IA64] per cpu MCA/INIT save areas · 82656e74
      Russ Anderson authored
        Linux currently has one MCA & INIT save area for saving
        stack and other data.  This patch creates per cpu MCA 
        save areas, so that each cpu can save its own MCA stack 
        data.  CPU register ar.k3 is used to hold a physical 
        address pointer to the cpuinfo structure.  The cpuinfo
        structure has a physical address pointer to the MCA save 
        area.  The MCA handler runs in physical mode and the 
        physical address pointer avoids the problems associated
        with doing the virtual to physical translation.
      
        The per MCA save areas replace the global areas defined
        in arch/ia64/kernel/mca.c for MCA processor state dump, 
        MCA stack, MCA stack frame, and MCA bspstore.
      
        The code to access those save areas is updated to use the
        per cpu save areas.
      
        No changes are made to the MCA flow, ie all the old locks
        are still in place.  The point of this patch is to establish
        the per cpu save areas.  Additional usage of the save areas,
        such as enabling concurrent INIT or MCA handling, will be
        the subject of other patches.
      Signed-off-by: default avatarRuss Anderson <rja@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      82656e74
    • Jack Steiner's avatar
      [IA64] Cachealign jiffies_64 to prevent unexpected aliasing in the caches. · 21718927
      Jack Steiner authored
      On large systems, system overhead on cpu 0 is higher than on other
      cpus. On a completely idle 512p system, the average amount of system time 
      on cpu 0 is 2.4%  and .15% on cpu 1-511.
      
      A second interesting data point is that if I run a busy-loop
      program on cpus 1-511, the system overhead on cpu 0 drops 
      significantly.
      
      I moved the timekeeper to cpu 1. The excessive system time moved
      to cpu 1 and the system time on cpu 0 dropped to .2%.
      
      Further investigation showed that the problem was caused by false
      sharing of the cacheline containing jiffies_64. On the kernel that
      I was running, both jiffies_64 & pal_halt share the same cacheline.
      Idle cpus are frequently accessing pal_halt. Minor kernel
      changes (including some of the debugging code that I used to find the 
      problem :-(  ) can cause variables to move & change the false sharing - the
      symptoms of the problem can change or disappear.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      21718927
    • Tony Luck's avatar
      Merge intel.com:/data/home/aegl/BK/work/config_generic_hardirqs · 3d37ec2c
      Tony Luck authored
      into intel.com:/data/home/aegl/BK/linux-ia64-test-2.6.11
      3d37ec2c
    • Jack Steiner's avatar
      [IA64-SGI] Add support for a future SGI chipset (shub2) 4of4 · cfab0690
      Jack Steiner authored
      Change the code that manages the LEDs so that it
      works on both shub1 & shub2.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      cfab0690
    • Jack Steiner's avatar
      [IA64-SGI] Add support for a future SGI chipset (shub2) 3of4 · d44aa798
      Jack Steiner authored
      Change the IPI & TLB flushing code so that it works on
      both shub1 & shub2.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      d44aa798
    • Jack Steiner's avatar
      [IA64-SGI] Add support for a future SGI chipset (shub2) 2of4 · 2ce29370
      Jack Steiner authored
      This patch adds the addresses of shub2 MMRS to the shub_mmr
      header file. During boot, a SAL call is made to determine the
      type of the shub. Platform initialization sets the appropriate
      MMR addresses for the platform.
      
      A new macro (is_shub1() & is_shub2()) can be used at runtime to
      determine the type of the shub.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      2ce29370
    • Jack Steiner's avatar
      [IA64-SGI] Add support for a future SGI chipset (shub2) 1of4 · 8ebb4697
      Jack Steiner authored
      This patch changes the SN macros for calulating the addresses
      of shub MMRs. Functionally, shub1 (current chipset) and shub2
      are very similar. The primary differences are in the addresses
      of MMRs and in the location of the NASID (node number) in
      a physical address. This patch adds the basic infrastructure
      for running a single binary kernel image on either shub1 or shub2.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      8ebb4697
    • Linus Torvalds's avatar
      Clean up open_exec()/kmalloc() error case handling. · f9286bcf
      Linus Torvalds authored
      It's a purely theoretical bug, since the kmalloc() failure that
      might "leak" file descriptors cannot actually happen (we do not
      ever fail small GFP_KERNEL allocations), but it's good to do
      things properly.
      
      Noted by Brad Spender.
      f9286bcf
    • Linus Torvalds's avatar
      Make sure VC resizing fits in s16. · ea75ccda
      Linus Torvalds authored
      Noted by Georgi Guninski
      ea75ccda
  2. 09 Dec, 2004 15 commits
  3. 08 Dec, 2004 15 commits