- 28 Aug, 2017 6 commits
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Johan Hovold authored
Make sure that the controller is runtime resumed when system suspending to avoid an external abort when accessing the interrupt registers: Unhandled fault: external abort on non-linefetch (0x1008) at 0xd025840a ... [<c05481a4>] (musb_default_readb) from [<c0545abc>] (musb_disable_interrupts+0x84/0xa8) [<c0545abc>] (musb_disable_interrupts) from [<c0546b08>] (musb_suspend+0x38/0xb8) [<c0546b08>] (musb_suspend) from [<c04a57f8>] (platform_pm_suspend+0x3c/0x64) This is easily reproduced on a BBB by enabling the peripheral port only (as the host port may enable the shared clock) and keeping it disconnected so that the controller is runtime suspended. (Well, you would also need to the not-yet-merged am33xx-suspend patches by Dave Gerlach to be able to suspend the BBB.) This is a regression that was introduced by commit 1c4d0b4e ("usb: musb: Remove pm_runtime_set_irq_safe") which allowed the parent glue device to runtime suspend and thereby exposed a couple of older issues: Register accesses without explicitly making sure the controller is runtime resumed during suspend was first introduced by commit c338412b ("usb: musb: unconditionally save and restore the context on suspend") in 3.14. Commit a1fc1920 ("usb: musb: core: make sure musb is in RPM_ACTIVE on resume") later started setting the RPM status to active during resume, and this was also implicitly relying on the parent always being active. Since commit 71723f95 ("PM / runtime: print error when activating a child to unactive parent") this now also results in the following warning: musb-hdrc musb-hdrc.0: runtime PM trying to activate child device musb-hdrc.0 but parent (47401400.usb) is not active This patch has been verified on 4.13-rc2, 4.12 and 4.9 using a BBB (the dsps glue would always be active also in 4.8). Fixes: c338412b ("usb: musb: unconditionally save and restore the context on suspend") Fixes: a1fc1920 ("usb: musb: core: make sure musb is in RPM_ACTIVE on resume") Fixes: 1c4d0b4e ("usb: musb: Remove pm_runtime_set_irq_safe") Cc: stable <stable@vger.kernel.org> # 4.8+ Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Daniel Mack <zonque@gmail.com> Cc: Dave Gerlach <d-gerlach@ti.com> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Bin Liu authored
The fifo memory allocation in mode_2_cfg[] doesn't utilize all the 4KB memory. Increse some endpoint fifo buffers to fully use all the 4KB memory. Now we can support more webcam usecases on DA8xx. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Bin Liu authored
There are multiple places in usb core or controller driver which returns -EMSGSIZE when a class driver queueing urb failed, so the "Message too long" log doesn't help much for understanding the error. Let the musb driver to specifically print a error message when musb_urb_enqueue() returns -EMSGSIZE. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Bin Liu authored
Print an error message with qh maxpacket size and hb_mult when hwep allocation failed, so we have a better idea why it is failed. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Bin Liu authored
Add helper function musb_ep_xfertype_string() to return the ep transfer type string. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Greg Kroah-Hartman authored
Merge tag 'usb-ci-v4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb into usb-next Peter writes: Chipidea changes for v4.14-rc1 - Add chipidea support at Nvidia SoCs - Improvement for extcon support - Some code refines
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- 25 Aug, 2017 1 commit
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Arnd Bergmann authored
Casting between an 'int' and a pointer causes a warning on 64-bit architectures in compile-testing this driver: drivers/phy/ralink/phy-ralink-usb.c: In function 'ralink_usb_phy_probe': drivers/phy/ralink/phy-ralink-usb.c:195:13: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] This changes the code to cast to uintptr_t instead. This is guaranteed to do what we want on all architectures and avoids the warning. Fixes: 2411a736 ("phy: ralink-usb: add driver for Mediatek/Ralink") Acked-by: John Crispin <john@phrozen.org> Tested-by Harvey Hunt <harvey.hunt@imgtec.com> Reviewed-by Harvey Hunt <harvey.hunt@imgtec.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 24 Aug, 2017 2 commits
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Thierry Reding authored
All of these Tegra SoC generations have a ChipIdea UDC IP block that can be used for device mode communication with a host. Implement rudimentary support that doesn't allow switching between host and device modes. Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Thierry Reding <treding@nvidia.com> [digetx@gmail.com: rebased patches and added DMA alignment quirk for Tegra20] Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
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Dmitry Osipenko authored
NVIDIA Tegra20 UDC can't cope with unaligned DMA and require a USB gadget quirk that avoids SKB buffer alignment to be set in order to make Ethernet Gadget working. Later Tegra generations do not require that quirk. Let's add a new platform data flag that allows to enable USB gadget quirk for platforms that require it. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
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- 22 Aug, 2017 15 commits
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Greg Kroah-Hartman authored
Merge tag 'phy-for-4.14_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.14 *) Add USB PHY driver for Ralink SoC *) Make phy-mt65xx-usb3 driver support PCIe and SATA phy *) Add mediatek directory and rename phy-mt65xx-usb3 to phy-mtk-tphy.c since it now supports USB3.0, PCIe and SATA PHYs *) Make sun4i-usb-phy driver support USB PHYs for A83T SoC *) Make phy-qcom-qmp driver support USB PHYs for IPQ8074 SoC *) Make rockchip-inno-usb2 driver support usb2-phy for rv1108 SoC *) Minor fixes in phy drivers Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usbGreg Kroah-Hartman authored
Felipe writes: usb: changes for v4.14 merge window Not a big pull request this time around. Only 49 non-merge commits. This pull request is, however, all over the place. Most of the changes are in the bdc driver adding support for USB Phy layer and PM. Renesas adds support for R-Car H3 ES2.0 and R-Car M3-W SoCs. Also here is PM_RUNTIME support for dwc3-keystone. UDC Core got a DMA unmap fix to make sure we only unmap requests that were, indeed, mapped. Other than these, we have a lot of cleanups, many of them adding 'const' to several places.
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Dan Carpenter authored
We want to timeout with try set to zero so this should be a pre-op instead of post-op. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Dan Carpenter authored
This line was indented further that it should have been. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Dan Carpenter authored
The "check" variable isn't necessarily initialized when we print it out in the debugging messages. It's a pretty haphazard affair and it doesn't matter very much what we initialize "check" to. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Shawn Lin authored
In order to silent the 'W=1' compile warning: drivers/phy/rockchip/phy-rockchip-typec.c: In function 'tcphy_get_mode': drivers/phy/rockchip/phy-rockchip-typec.c:625:7: warning: variable 'dfp' set but not used [-Wunused-but-set-variable] Cc: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Frank Wang authored
This adds support usb2-phy for rv1108 SoCs and amend phy Documentation. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Frank Wang authored
Add otg-mux property to support multiplexed interrupt in otg-port on some Rockchip SoC (e.g RV1108). Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Frank Wang authored
The otg-id/otg-bvalid/linestate interrupts are multiplexed together in otg-port on some Rockchip SoC (e.g RV1108), this patch add support for it. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Frank Wang authored
Add rockchip,usbgrf property to support the registers of usb-phy that are distributed in grf and usbgrf on some special Rockchip SoCs (e.g RV1108). Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Frank Wang authored
The registers of usb-phy are distributed in grf and usbgrf on some Rockchip SoCs (e.g RV1108), this patch add a new rockchip,usbgrf property to support this companion grf design. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chen-Yu Tsai authored
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. The phy initialization procedure is very different from other SoCs, but the PMU bits are the same, with additional bits for HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chen-Yu Tsai authored
On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires two clocks instead of one. On all Allwinner SoCs that share the common USB PHY design supported by the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there is at most one HSIC PHY, typically the last. In this patch we take advantage of these known constraints and store an index in the compatible-string-related config structure describing which PHY is HSIC, needing the extra hsic_12M clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chen-Yu Tsai authored
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. Add a compatible string for it, and describe the needed properties. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chen-Yu Tsai authored
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu regions, clocks, resets, and optional vbus properties. These were not described when the H3 compatible string was added. Fixes: 626a630e ("phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 20 Aug, 2017 13 commits
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John Crispin authored
Add a driver to setup the USB phy on Mediatek/Ralink SoCs. The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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John Crispin authored
Add a binding for the USB phy on Mediatek/Ralink SoCs. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
reduce the boilerplate code to get the specific data Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
add support for PCIe and SATA, also add some new compatibles. due to phy-mt65xx-usb.txt holds the bindings for all mediatek SoCs with T-PHY controller, change the name to phy-mtk-tphy.txt to reflect that. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Ryder Lee authored
This patch adds SATA setting part. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Ryder Lee authored
This patch adds PCIe PHY setting part. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Roger Quadros authored
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdfSigned-off-by: Roger Quadros <rogerq@ti.com> [nsekhar@ti.com: add exact TRM version to commit text] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Vivek Gautam authored
Fixing the clk enable failure path in qcom_qmp_phy_init() and cleanup the reset control deassertion failure path in qcom_qmp_phy_com_init(). Fixes: e78f3d15 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Varadarajan Narayanan authored
Add definitions required to enable QMP phy support for IPQ8074. Signed-off-by: smuthayy <smuthayy@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Varadarajan Narayanan authored
Presently, the phy pipe clock's name is assumed to be either usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the phy lane's number). However, this will not work if an SoC has more than one instance of the phy. Hence, instead of assuming the name of the clock, fetch it from the DT. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Varadarajan Narayanan authored
IPQ8074 uses QMP PHY controller that provides support to PCIe and USB. Adding DT binding information for the same. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Varadarajan Narayanan authored
The PHY outputs a clock that will act as the parent for the PHY's pipe clock. Add the name of this clock to the lane's DT node. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 18 Aug, 2017 3 commits
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Dmitry Osipenko authored
That quirk is required to make USB Ethernet gadget working on HW that can't cope with unaligned DMA. For some reason only f_ncm sets up that quirk, let's setup it directly in u_ether so other network models would have that quirk applied as well. All network models have been tested with ChipIdea UDC driver on NVIDIA Tegra20 SoC that require DMA to be aligned. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Stephen Warren authored
When the gadget serial device has no associated TTY, do not pass any received data into the TTY layer for processing; simply drop it instead. This prevents the TTY layer from calling back into the gadget serial driver, which will then crash in e.g. gs_write_room() due to lack of gadget serial device to TTY association (i.e. a NULL pointer dereference). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Alan Stern authored
The usb_add_gadget_udc_release() routine in the USB gadget core will sometimes but not always call the gadget's release function when an error occurs. More specifically, if the struct usb_udc allocation fails then the release function is not called, and for other errors it is. As a result, users of this routine cannot know whether they need to deallocate the memory containing the gadget structure following an error. This leads to unavoidable memory leaks or double frees. This patch fixes the problem by splitting the existing device_register() call into device_initialize() and device_add(), and doing the udc allocation in between. That way, even if the allocation fails it is still possible to call device_del(), and so the release function will be always called following an error. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Reported-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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