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- 07 Jul, 2022 29 commits
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AngeloGioacchino Del Regno authored
All devices of the Cherry platform have a MT6360 sub-pmic, providing two LDOs. Add the required node to enable the PMIC but without regulators yet, as these will be added in a later commit. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220704101321.44835-10-angelogioacchino.delregno@collabora.comSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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AngeloGioacchino Del Regno authored
Add USB functionality by enabling the required PHYs and the XHCI controllers. This enables all of the supported USB ports on the Cherry boards. Please note that u3phy1 also enables u3port1, which is configured to be a PCI-Express PHY for the second PCIe controller that is found on the MT8195 SoC, which will be enabled in a later commit. Signed-off-by:
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AngeloGioacchino Del Regno authored
This platform uses eight I2C controllers and one SPI controller: in preparation for enabling devices attached to these controllers, add basic configuration to enable the busses. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add gpio-line-names to document GPIO names and add the default basic pin configuration to allow lower power operation by setting appropriate state on the unused pins. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add mtk-sd controller and pin configuration to enable the internal eMMC storage: now it is possible to mount a rootfs located at the internal storage. Signed-off-by:
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AngeloGioacchino Del Regno authored
To allow MT6359 peripherals to trigger interrupts and the driver to safely handle them, assign the right interrupt line for the Cherry platform to the MT6359 PMIC node. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the regulators layout for this platform, including the basic power rails controlled by the EC (and/or always on). Moreover, include the MT6359 PMIC devicetree and add some configuration for its regulators, essential to keep the machine alive after booting. Signed-off-by:
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AngeloGioacchino Del Regno authored
Introduce the MT8195 Cherry Chromebook platform, including three revisions of Cherry Tomato boards. This basic configuration allows to boot Linux on all board revisions and get a serial console from a ramdisk. Signed-off-by:
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AngeloGioacchino Del Regno authored
Document board compatibles for the MT8195 Cherry platform's Tomato Chromebooks, at the time of writing composed of four revisions (r1, r2, r3-r4). Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220704101321.44835-2-angelogioacchino.delregno@collabora.comSigned-off-by:
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Nícolas F. R. A. Prado authored
Add support for the SPI NOR flash memory present on the Asurada platform. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220629155956.1138955-20-nfraprado@collabora.comSigned-off-by:
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Nícolas F. R. A. Prado authored
Enable support for the SCP co-processor present on MT8192. It is used as part of the video encoding and decoding processes. A region of memory is carved out for its use, and remoteproc setup for communication with the ChromeOS EC. Signed-off-by:
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Nícolas F. R. A. Prado authored
Enable both MMC controllers present on Asurada. MMC0 is for non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't used on all machines, but in those cases the CD interrupt is never triggered and thus it is basically as if it was disabled. Signed-off-by:
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Nícolas F. R. A. Prado authored
The Asurada platform uses regulators from MT6315 PMICs acessible through SPMI. Add support for them. Signed-off-by:
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Nícolas F. R. A. Prado authored
MT6359 is the primary PMIC present on the Asurada platform. Include its dtsi and configure properties specific for the platform. Signed-off-by:
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Nícolas F. R. A. Prado authored
Enable MT8192's PCIe controller and add support for the MT7921e WiFi card that is present on that bus for the Asurada platform. Signed-off-by:
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Nícolas F. R. A. Prado authored
Enable XHCI controller on the Asurada platform. This allows the use of the USB ports, and therefore a rootfs can be loaded and a usable shell reached from a live USB image. Signed-off-by:
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Nícolas F. R. A. Prado authored
The Spherion board has keyboard backlight controlled by the PWM signal generated by the ChromeOS EC. Enable PWM output for ChromeOS EC and add a PWM controlled LED node for the keyboard backlight. Signed-off-by:
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Nícolas F. R. A. Prado authored
All machines of the Asurada platform have a touchscreen at address 0x10 in the I2C0 bus, but the devices vary: Spherion has the Elan eKTH3500 touchscreen, while Hayato has a generic HID-over-i2c touchscreen. Add common support for the touchscreens on the platform and the specifics in each board file. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is connected to the I2C2 bus and has address 0x15. Signed-off-by:
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Nícolas F. R. A. Prado authored
The Asurada platform has a Google Security Chip connected to the SPI5 bus. It runs the cr50 firmware and provides TPM functionality. Add support for it. Signed-off-by:
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Nícolas F. R. A. Prado authored
Chromebooks' embedded keyboards differ from standard layouts for the top row in that they have shortcuts in place of the standard function keys. Map these keys to achieve the functionality that is pictured on the printouts. There's a minor difference between the keys present on Hayato, which uses an older layout, and Spherion, which uses a newer one. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add support for the ChromeOS Embedded Controller present on the Asurada platform. It is connected through the SPI1 bus and offers several functionalities: base detection, PWM controller, I2C tunneling, regulators, Type-C connector management, keyboard and Smart Battery Metrics (SBS). Signed-off-by:
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Nícolas F. R. A. Prado authored
The Asurada platform has five I2C controllers and two SPI controllers that are used. In preparation for enabling the devices connected to these controllers, enable and configure their busses. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add system-wide power supplies present on all of the boards in the Asurada family. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add the gpio-line-names property to gpio-controller in order to document the usage of GPIOs on the Asurada platform. Signed-off-by:
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Nícolas F. R. A. Prado authored
Introduce the MT8192 Asurada Chromebook platform, including the Asurada Spherion and Asurada Hayato boards. This is enough configuration to get serial output working on Spherion and Hayato. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add binding for the Google Hayato board. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220629155956.1138955-3-nfraprado@collabora.comSigned-off-by:
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Nícolas F. R. A. Prado authored
Add binding for the Google Spherion board, which is used for Acer Chromebook 514 (CB514-2H). Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a phandle to the MT8183_POWER_DOMAIN_MFG_ASYNC power domain and assign the GPU VSRAM supply to this in mt8183-kukui: this allows to keep the sram powered up while the GPU is used. Signed-off-by:
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- 22 Jun, 2022 11 commits
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Allen-KH Cheng authored
This commit adds dt-binding documentation for the MediaTek MT8186 reference board. Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by:
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Allen-KH Cheng authored
Add mt8186 pericfg compatible to binding document. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the maintenance interrupt for GIC-400. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a node for the pinctrl controller found on MT6795 but without configuration for any pin, as that's expected to be done in the machine-specific devicetrees. Signed-off-by:
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AngeloGioacchino Del Regno authored
This SoC features an ARM CCI-400 IP: add the required node and assign the cci control ports to the CPU cores. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the timer node, enabling two GPTs, of which one will be used as sched_clock. Signed-off-by:
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AngeloGioacchino Del Regno authored
Remove the RTC and UART fixed clocks, as these were introduced to temporarily provide a dummy clock to devices: since the two 26M/32K fixed oscillators clocks (which do really exist in the SoC) have been added, there's no reason to keep the aforementioned (and now redundant) dummies in this devicetree. In order to remove the uart dummy clock, it was necessary to also reassign the clock of all UART nodes to clk26m. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies. Signed-off-by:
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AngeloGioacchino Del Regno authored
At least on commercial devices like some smartphones, the bootloader will initialize the SoC watchdog and set it to reboot the board when it times out. The last pet that this watchdog is getting is right before booting the kernel and left it enabled as a protection against boot failure: this means that Linux is expected to initialize this device and pet as soon as possible, or it will bark and reset the AP. In order to prevent that, add the required watchdog node as default enabled: this will have no side effects on boards that are not performing the aforementioned watchdog setup before booting Linux. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the required nodes to enable the PMU on this SoC. Signed-off-by:
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AngeloGioacchino Del Regno authored
This SoC is HMP and has two clusters with four Cortex-A53 cores each: declare a cpu map and, while at it, also add the next-level-cache properties. Signed-off-by:
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