- 17 Oct, 2022 36 commits
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Previous adjustment missefd one spot. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-35-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-34-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-33-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-32-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-31-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-30-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. qcom-sdx55-telit-fn980-tlb.dtb: pinctrl@f100000: 'pcie_ep_clkreq_default', 'pcie_ep_perst_default', 'pcie_ep_wake_default' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-29-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-28-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-27-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-26-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Certain pins, like SDcard related, do not have functions and such should not be required. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-25-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-24-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-23-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-22-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-21-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Certain pins, like SDcard related, do not have functions and such should not be required. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-20-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-19-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-18-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The MSM8226 pinctrl driver supports input-enable, blsp_i2c4, blsp_uart4 and sdc3 functions and DTS already uses it: qcom-msm8226-samsung-s3ve3g.dtb: pinctrl@fd510000: 'blsp1-i2c1', 'blsp1-i2c2', 'blsp1-i2c3', 'blsp1-i2c4', 'blsp1-i2c5' ... qcom-apq8026-lg-lenok.dtb: pinctrl@fd510000: touch-state: 'oneOf' conditional failed, one must be fixed: 'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-17-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-16-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-15-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-14-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-13-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-12-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
One pinxmux node can have more than 4 pins to configure: ['gpio1', 'gpio3', 'gpio4', 'gpio5', 'gpio6', 'gpio7', 'gpio8', 'gpio10', 'gpio11', 'gpio12', 'gpio13', 'gpio14', 'gpio15', 'gpio17'] is too long Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-11-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The pin controller driver has BLSP functions from 0 to 5, not 1 to 6. Add missing blsp0_i2c, blsp0_spi (already used in ipq6018-cp01-c1) and blsp0_uart. Drop blsp6_i2c and blsp6_spi. This fixes dtbs_check warning: ipq6018-cp01-c1.dtb: pinctrl@1000000: spi-0-state: 'oneOf' conditional failed, one must be fixed: 'bias-pull-down', 'drive-strength', 'function', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' 'blsp0_spi' is not one of ['adsp_ext', 'alsp_int', ..... Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-10-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The IPQ6018 pinctrl driver supports qpic_pad and DTS already uses it: 'qpic_pad' is not one of ['adsp_ext', 'alsp_int', 'atest_bbrx0', ... Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-9-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Certain pins, like SDcard related, do not have functions and such should not be required. Add a check for this in common Qualcomm TLMM pin controller schema. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-8-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The existing SC7280 LPASS pin controller nodes use bias-bus-hold and input-enable, so allow them. Squash also blank lines for readability. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-13-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The existing SC7280 LPASS pin controller nodes use bias-bus-hold, so allow it. Squash also blank lines for readability. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-12-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-11-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. qcom/qrb5165-rb5.dtb: pinctrl@33c0000: wsa-swr-active-pins: 'pins' is a required property Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-10-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-9-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-8-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Fix double ']' in GPIO pattern to properly match "pins" property. Otherwise schema for pins state fails. Fixes: 4faa4e73 ("dt-bindings: pinctrl: qcom: Add sm8450 lpass lpi pinctrl bindings") Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-7-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Krzysztof Kozlowski authored
Fix double ']' in GPIO pattern to properly match "pins" property. Otherwise schema for pins state fails. Fixes: 958bb025 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings") Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-6-krzysztof.kozlowski@linaro.orgSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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- 16 Oct, 2022 4 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/crng/randomLinus Torvalds authored
Pull more random number generator updates from Jason Donenfeld: "This time with some large scale treewide cleanups. The intent of this pull is to clean up the way callers fetch random integers. The current rules for doing this right are: - If you want a secure or an insecure random u64, use get_random_u64() - If you want a secure or an insecure random u32, use get_random_u32() The old function prandom_u32() has been deprecated for a while now and is just a wrapper around get_random_u32(). Same for get_random_int(). - If you want a secure or an insecure random u16, use get_random_u16() - If you want a secure or an insecure random u8, use get_random_u8() - If you want secure or insecure random bytes, use get_random_bytes(). The old function prandom_bytes() has been deprecated for a while now and has long been a wrapper around get_random_bytes() - If you want a non-uniform random u32, u16, or u8 bounded by a certain open interval maximum, use prandom_u32_max() I say "non-uniform", because it doesn't do any rejection sampling or divisions. Hence, it stays within the prandom_*() namespace, not the get_random_*() namespace. I'm currently investigating a "uniform" function for 6.2. We'll see what comes of that. By applying these rules uniformly, we get several benefits: - By using prandom_u32_max() with an upper-bound that the compiler can prove at compile-time is ≤65536 or ≤256, internally get_random_u16() or get_random_u8() is used, which wastes fewer batched random bytes, and hence has higher throughput. - By using prandom_u32_max() instead of %, when the upper-bound is not a constant, division is still avoided, because prandom_u32_max() uses a faster multiplication-based trick instead. - By using get_random_u16() or get_random_u8() in cases where the return value is intended to indeed be a u16 or a u8, we waste fewer batched random bytes, and hence have higher throughput. This series was originally done by hand while I was on an airplane without Internet. Later, Kees and I worked on retroactively figuring out what could be done with Coccinelle and what had to be done manually, and then we split things up based on that. So while this touches a lot of files, the actual amount of code that's hand fiddled is comfortably small" * tag 'random-6.1-rc1-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random: prandom: remove unused functions treewide: use get_random_bytes() when possible treewide: use get_random_u32() when possible treewide: use get_random_{u8,u16}() when possible, part 2 treewide: use get_random_{u8,u16}() when possible, part 1 treewide: use prandom_u32_max() when possible, part 2 treewide: use prandom_u32_max() when possible, part 1
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Linus Torvalds authored
Merge tag 'perf-tools-for-v6.1-2-2022-10-16' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux Pull more perf tools updates from Arnaldo Carvalho de Melo: - Use BPF CO-RE (Compile Once, Run Everywhere) to support old kernels when using bperf (perf BPF based counters) with cgroups. - Support HiSilicon PCIe Performance Monitoring Unit (PMU), that monitors bandwidth, latency, bus utilization and buffer occupancy. Documented in Documentation/admin-guide/perf/hisi-pcie-pmu.rst. - User space tasks can migrate between CPUs, so when tracing selected CPUs, system-wide sideband is still needed, fix it in the setup of Intel PT on hybrid systems. - Fix metricgroups title message in 'perf list', it should state that the metrics groups are to be used with the '-M' option, not '-e'. - Sync the msr-index.h copy with the kernel sources, adding support for using "AMD64_TSC_RATIO" in filter expressions in 'perf trace' as well as decoding it when printing the MSR tracepoint arguments. - Fix program header size and alignment when generating a JIT ELF in 'perf inject'. - Add multiple new Intel PT 'perf test' entries, including a jitdump one. - Fix the 'perf test' entries for 'perf stat' CSV and JSON output when running on PowerPC due to an invalid topology number in that arch. - Fix the 'perf test' for arm_coresight failures on the ARM Juno system. - Fix the 'perf test' attr entry for PERF_FORMAT_LOST, adding this option to the or expression expected in the intercepted perf_event_open() syscall. - Add missing condition flags ('hs', 'lo', 'vc', 'vs') for arm64 in the 'perf annotate' asm parser. - Fix 'perf mem record -C' option processing, it was being chopped up when preparing the underlying 'perf record -e mem-events' and thus being ignored, requiring using '-- -C CPUs' as a workaround. - Improvements and tidy ups for 'perf test' shell infra. - Fix Intel PT information printing segfault in uClibc, where a NULL format was being passed to fprintf. * tag 'perf-tools-for-v6.1-2-2022-10-16' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (23 commits) tools arch x86: Sync the msr-index.h copy with the kernel sources perf auxtrace arm64: Add support for parsing HiSilicon PCIe Trace packet perf auxtrace arm64: Add support for HiSilicon PCIe Tune and Trace device driver perf auxtrace arm: Refactor event list iteration in auxtrace_record__init() perf tests stat+json_output: Include sanity check for topology perf tests stat+csv_output: Include sanity check for topology perf intel-pt: Fix system_wide dummy event for hybrid perf intel-pt: Fix segfault in intel_pt_print_info() with uClibc perf test: Fix attr tests for PERF_FORMAT_LOST perf test: test_intel_pt.sh: Add 9 tests perf inject: Fix GEN_ELF_TEXT_OFFSET for jit perf test: test_intel_pt.sh: Add jitdump test perf test: test_intel_pt.sh: Tidy some alignment perf test: test_intel_pt.sh: Print a message when skipping kernel tracing perf test: test_intel_pt.sh: Tidy some perf record options perf test: test_intel_pt.sh: Fix return checking again perf: Skip and warn on unknown format 'configN' attrs perf list: Fix metricgroups title message perf mem: Fix -C option behavior for perf mem record perf annotate: Add missing condition flags for arm64 ...
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Linus Torvalds authored
Merge tag 'kbuild-fixes-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild Pull Kbuild fixes from Masahiro Yamada: - Fix CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y compile error for the combination of Clang >= 14 and GAS <= 2.35. - Drop vmlinux.bz2 from the rpm package as it just annoyingly increased the package size. - Fix modpost error under build environments using musl. - Make *.ll files keep value names for easier debugging - Fix single directory build - Prevent RISC-V from selecting the broken DWARF5 support when Clang and GAS are used together. * tag 'kbuild-fixes-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: lib/Kconfig.debug: Add check for non-constant .{s,u}leb128 support to DWARF5 kbuild: fix single directory build kbuild: add -fno-discard-value-names to cmd_cc_ll_c scripts/clang-tools: Convert clang-tidy args to list modpost: put modpost options before argument kbuild: Stop including vmlinux.bz2 in the rpm's Kconfig.debug: add toolchain checks for DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT Kconfig.debug: simplify the dependency of DEBUG_INFO_DWARF4/5
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