- 25 Feb, 2022 5 commits
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Minghao Chi (CGEL ZTE) authored
Use of_device_get_match_data() instead of open-coding it. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220214020626.1714696-1-chi.minghao@zte.com.cnSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Samuel Holland authored
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-4-samuel@sholland.orgSigned-off-by:
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Andre Przywara authored
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
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Samuel Holland authored
.disc_thresh is not used when .type = sun50i_h6_phy, so providing a value for it is misleading. Signed-off-by:
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Samuel Holland authored
D1 features one OTG port and one host port, like the A64 SoC, so its USB PHY supports the same set of properties. Add the new compatible to the existing binding. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220203013558.11490-1-samuel@sholland.orgSigned-off-by:
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- 24 Feb, 2022 3 commits
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Yifeng Zhao authored
This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by:
Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Tested-by:
Peter Geis <pgwipeout@gmail.com> Tested-by:
Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.comSigned-off-by:
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Yifeng Zhao authored
Add the compatible strings for the Naneng combo PHY found on rockchip SoC. Reviewed-by:
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Johan Jonker authored
Add Naneng combo phy register compatible. Acked-by:
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- 22 Feb, 2022 7 commits
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Krzysztof Kozlowski authored
Convert the Samsung Exynos USB 3.0 DRD PHY bindings to DT schema format. Except the conversion, add also vbus-supply and vbus-boost-supply properties which were already used by the driver and DTS. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by:
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Krzysztof Kozlowski authored
The I2C interface for Samsung Exynos SoC SATA phy is a very simple and limited, so move it to trivial devices. Signed-off-by:
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Krzysztof Kozlowski authored
Convert the Samsung Exynos5250 SoC SATA PHY bindings to DT schema format. Signed-off-by:
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Krzysztof Kozlowski authored
Convert the Samsung SoC USB 2.0 PHY bindings to DT schema format. Except the conversion, add also vbus-supply property which was already used by the driver and DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Convert the Samsung SoC DisplayPort PHY bindings to DT schema format. Signed-off-by:
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Krzysztof Kozlowski authored
Convert the Samsung SoC MIPI CSIS/DSIM DPHY bindings to DT schema format. Signed-off-by:
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Krzysztof Kozlowski authored
The Exynos5440 PCIe phy support was removed in commit 496db029 ("phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY") (with its own bindings), so drop the old bindings. Signed-off-by:
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- 08 Feb, 2022 3 commits
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Sankeerth Billakanti authored
Some legacy eDP sinks may not support SSC. The support for SSC is indicated through an opts flag from the controller driver. This change will enable SSC only if the sink supports it. Signed-off-by:
Sankeerth Billakanti <quic_sbillaka@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20220207161612.REPOST.v1.3.Ie81d594ec2327dae6410db359cc492484bab171f@changeidSigned-off-by:
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Sankeerth Billakanti authored
The sc7280 platform supports native eDP controller and PHY. This change will add support for the eDP PHY on sc7280. Signed-off-by:
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Sankeerth Billakanti authored
Add compatible string for the supported eDP PHY on sc7280 platform. Signed-off-by:
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- 07 Feb, 2022 2 commits
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Aswath Govindraju authored
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Reviewed-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220128072642.29188-1-a-govindraju@ti.comSigned-off-by:
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Vinod Koul authored
Merge phy fixes for 5.17 into next branch to resolve the conflict between fixes and next for upcoming patches
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- 02 Feb, 2022 2 commits
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Allen-KH Cheng authored
This commit adds dt-binding documentation of T-Phy for Mediatek MT8186 SoC Platform. Signed-off-by:
Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> Link: https://lore.kernel.org/r/20220128062050.23978-6-allen-kh.cheng@mediatek.comSigned-off-by:
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Liu Ying authored
The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE parameter's unit is Unit Interval(UI) and the minimum value is 8. Also, kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy mentions that it should be in UI. However, the dphy core driver wrongly sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds. So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE parameter's minimum value according to the D-PHY specification. I'm assuming that all impacted custom drivers shall program values in TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY specification mentions that the frequency of TxByteClkHS is exactly 1/8 the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant custom driver code is changed to program those values as DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then. Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, as I don't have the hardwares. Fixes: 2ed86999 ("phy: Add MIPI D-PHY configuration options") Tested-by: Liu Ying <victor.liu@nxp.com> # RM67191 DSI panel on i.MX8mq EVK Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Guido Günther <agx@sigxcpu.org> # Librem 5 (imx8mq) with it's rather picky panel Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20220124024007.1465018-1-victor.liu@nxp.comSigned-off-by:
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- 27 Jan, 2022 11 commits
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Wan Jiabing authored
Fix following coccicheck warning: ./drivers/phy/mediatek/phy-mtk-tphy.c:994:6-29: duplicated argument to && or || The efuse_rx_imp is duplicate. Here should be efuse_tx_imp. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Acked-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220107025050.787720-1-wanjiabing@vivo.comSigned-off-by:
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David Heidelberg authored
Conversion of Qualcomm USB HS phy documentation to yaml. Signed-off-by:
David Heidelberg <david@ixit.cz> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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Amjad Ouled-Ameur authored
Use reset_control_rearm() call if an error occurs in case phy_meson8b_usb2_power_on() fails after reset() has been called, or in case phy_meson8b_usb2_power_off() is called i.e the resource is no longer used and the reset line may be triggered again by other devices. reset_control_rearm() keeps use of triggered_count sane in the reset framework, use of reset_control_reset() on shared reset line should be balanced with reset_control_rearm(). Signed-off-by:
Amjad Ouled-Ameur <aouledameur@baylibre.com> Reported-by:
Jerome Brunet <jbrunet@baylibre.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220111095255.176141-4-aouledameur@baylibre.comSigned-off-by:
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Amjad Ouled-Ameur authored
Use the existing dev_err_probe() helper instead of open-coding the same operation. Signed-off-by:
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Amjad Ouled-Ameur authored
Use reset_control_rearm() call if an error occurs in case phy_meson_gxl_usb2_init() fails after reset() has been called ; or in case phy_meson_gxl_usb2_exit() is called i.e the resource is no longer used and the reset line may be triggered again by other devices. reset_control_rearm() keeps use of triggered_count sane in the reset framework. Therefore, use of reset_control_reset() on shared reset line should be balanced with reset_control_rearm(). Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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Geert Uytterhoeven authored
The Freescale/NXP i.MX8 USB3, MIPI DSI, and PCIE PHYs are only present on the NXP i.MX8 family of SoCs. Hence wrap the config symbols for these PHYs inside a check for ARCH_MXC && ARM64, to prevent asking the user about these drivers when configuring a kernel without NXP i.MX SoC family support. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Guido Günther <agx@sigxcpu.org> Link: https://lore.kernel.org/r/393868affd830016d35f0d9aba32ccd7098c8073.1641987369.git.geert+renesas@glider.beSigned-off-by:
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Dan Carpenter authored
This error path needs to decrement "usbphyc->n_pll_cons.counter" before returning. Fixes: 5b1af712 ("phy: stm32: rework PLL Lock detection") Signed-off-by:
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Luca Weiss authored
Add compatible for MSM8953 QUSB2 device which reuses MSM8996 configuration. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Acked-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220112194118.178026-3-luca@z3ntu.xyzSigned-off-by:
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Luca Weiss authored
Document the compatible string used for the qusb2 phy in msm8953. Signed-off-by:
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Marcel Ziswiler authored
Sort includes alphabethically and add a new line before the dt-bindings one as usually done. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Link: https://lore.kernel.org/r/20220113090321.119880-1-marcel@ziswiler.comSigned-off-by:
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Robert Hancock authored
TX_PROT_BUS_WIDTH and RX_PROT_BUS_WIDTH are single registers with separate bit fields for each lane. The code in xpsgtr_phy_init_sgmii was not preserving the existing register value for other lanes, so enabling the PHY in SGMII mode on one lane zeroed out the settings for all other lanes, causing other PS-GTR peripherals such as USB3 to malfunction. Use xpsgtr_clr_set to only manipulate the desired bits in the register. Fixes: 4a33bea0 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Signed-off-by:
Robert Hancock <robert.hancock@calian.com> Acked-by:
Michal Simek <michal.simek@xilinx.com> Reviewed-by:
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- 24 Jan, 2022 4 commits
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Ansuel Smith authored
Convert latch function to readl pool macro to tidy things up. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220117002641.26773-2-ansuelsmth@gmail.comSigned-off-by:
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Ansuel Smith authored
Convert some define to BITFIELD macro to tidy things up. Signed-off-by:
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Dan Carpenter authored
There are two bugs in the error handling: 1: If devm_of_phy_provider_register() fails then there was no cleanup. 2: The error handling called of_node_put(child) improperly leading to a use after free. We are only holding the reference inside the loop so the last two gotos after the loop lead to a use after free bug. Fix this by cleaning up the partial allocations (or partial iterations) in the loop before doing the goto. Fixes: a43f72ae ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by:
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Kishon Vijay Abraham I authored
_get_table_maxdiv() tries to access "clk_div_table" array out of bound defined in phy-j721e-wiz.c. Add a sentinel entry to prevent the following global-out-of-bounds error reported by enabling KASAN. [ 9.552392] BUG: KASAN: global-out-of-bounds in _get_maxdiv+0xc0/0x148 [ 9.558948] Read of size 4 at addr ffff8000095b25a4 by task kworker/u4:1/38 [ 9.565926] [ 9.567441] CPU: 1 PID: 38 Comm: kworker/u4:1 Not tainted 5.16.0-116492-gdaadb3bd-dirty #360 [ 9.576242] Hardware name: Texas Instruments J721e EVM (DT) [ 9.581832] Workqueue: events_unbound deferred_probe_work_func [ 9.587708] Call trace: [ 9.590174] dump_backtrace+0x20c/0x218 [ 9.594038] show_stack+0x18/0x68 [ 9.597375] dump_stack_lvl+0x9c/0xd8 [ 9.601062] print_address_description.constprop.0+0x78/0x334 [ 9.606830] kasan_report+0x1f0/0x260 [ 9.610517] __asan_load4+0x9c/0xd8 [ 9.614030] _get_maxdiv+0xc0/0x148 [ 9.617540] divider_determine_rate+0x88/0x488 [ 9.622005] divider_round_rate_parent+0xc8/0x124 [ 9.626729] wiz_clk_div_round_rate+0x54/0x68 [ 9.631113] clk_core_determine_round_nolock+0x124/0x158 [ 9.636448] clk_core_round_rate_nolock+0x68/0x138 [ 9.641260] clk_core_set_rate_nolock+0x268/0x3a8 [ 9.645987] clk_set_rate+0x50/0xa8 [ 9.649499] cdns_sierra_phy_init+0x88/0x248 [ 9.653794] phy_init+0x98/0x108 [ 9.657046] cdns_pcie_enable_phy+0xa0/0x170 [ 9.661340] cdns_pcie_init_phy+0x250/0x2b0 [ 9.665546] j721e_pcie_probe+0x4b8/0x798 [ 9.669579] platform_probe+0x8c/0x108 [ 9.673350] really_probe+0x114/0x630 [ 9.677037] __driver_probe_device+0x18c/0x220 [ 9.681505] driver_probe_device+0xac/0x150 [ 9.685712] __device_attach_driver+0xec/0x170 [ 9.690178] bus_for_each_drv+0xf0/0x158 [ 9.694124] __device_attach+0x184/0x210 [ 9.698070] device_initial_probe+0x14/0x20 [ 9.702277] bus_probe_device+0xec/0x100 [ 9.706223] deferred_probe_work_func+0x124/0x180 [ 9.710951] process_one_work+0x4b0/0xbc0 [ 9.714983] worker_thread+0x74/0x5d0 [ 9.718668] kthread+0x214/0x230 [ 9.721919] ret_from_fork+0x10/0x20 [ 9.725520] [ 9.727032] The buggy address belongs to the variable: [ 9.732183] clk_div_table+0x24/0x440 Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Cc: stable@vger.kernel.org # v5.10+ Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20220117110108.4117-1-kishon@ti.comSigned-off-by:
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- 23 Jan, 2022 3 commits
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Al Cooper authored
The previous commit 4b402fa8 ("phy: phy-brcm-usb: support PHY on the BCM4908") added a second "default" line for ARCH_BCM_4908 above the original "default" line for ARCH_BRCMSTB. When two "default" lines are used, only the first is used and this change stopped the PHY_BRCM_USB option for being enabled for ARCH_BRCMSTB. The fix is to use one "default line with "||". Fixes: 4b402fa8 ("phy: phy-brcm-usb: support PHY on the BCM4908") Signed-off-by:
Al Cooper <alcooperx@gmail.com> Acked-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211201180653.35097-4-alcooperx@gmail.comSigned-off-by:
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Al Cooper authored
The PHY client driver does a phy_exit() call on suspend or rmmod and the PHY driver needs to know the difference because some clocks need to be kept running for suspend but can be shutdown on unbind/rmmod (or if there are no PHY clients at all). The fix is to use a PM notifier so the driver can tell if a PHY client is calling exit() because of a system suspend or a driver unbind/rmmod. Signed-off-by:
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Linus Torvalds authored
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