- 24 Mar, 2021 33 commits
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Matthew Auld authored
For the PTEs we get an LM bit, to signal whether the page resides in SMEM or LMEM. BSpec: 45040 v2: just use gen8_pte_encode for dg1 Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Signed-off-by:
Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Zbigniew Kempczyński authored
In preparation for Xe HP multi-tile architecture with multiple memory regions, we need to be able differentiate multiple instances of device local-memory. Note that the region name is just to give it a human friendly identifier, instead of using class/instance which also uniquely identifies the region. So far the region name is only for our own internal debugging in the kernel(like in the selftests), or debugfs which prints the list of regions, including the regions name. v2: add commentary for our current region name use Signed-off-by:
Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Signed-off-by:
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Chris Wilson authored
We have not seen an occurrence of the false restart state recenty, and if we did see such an event from inside engine-reset, it would deadlock on trying to suspend the tasklet to read the register state (from inside the tasklet). Instead, we inspect the context state before submission which will alert us to any issues prior to execution on HW. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210201164222.14455-1-chris@chris-wilson.co.ukSigned-off-by:
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Chris Wilson authored
Instead of copying the whole table to each category (mocs, l3cc), use a single table with a pointer to it if the category is enabled. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210201100448.9802-1-chris@chris-wilson.co.ukSigned-off-by:
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Chris Wilson authored
As soon as we mark a request as completed, it may be retired. So when cancelling a request and marking it complete, make sure we first keep a reference to the request. Signed-off-by:
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Michel Thierry authored
Prefer allocating the cmd ring from LMEM on dgfx. Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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Matthew Auld authored
Prefer allocating the engine scratch from LMEM on dgfx. v2: flatten the chain Signed-off-by:
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Matthew Auld authored
Prefer allocating the context from LMEM on dgfx. Based on a patch from Michel Thierry. v2: flatten the chain Signed-off-by:
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Imre Deak authored
On DG1 A0/B0 steppings the first 1MB of local memory must be reserved. One reason for this is that the 0xA0000-0xB0000 range is not accessible by the display, probably since this region is redirected to another memory location for legacy VGA compatibility. BSpec: 50586 Testcase: igt/kms_big_fb/linear-64bpp-rotate-0 v2: - Reserve the memory on B0 as well. v3: replace DRM_DEBUG/DRM_ERROR with drm_dbg/drm_err v4: fix the insanity Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Abdiel Janulgue authored
In the following patch we need to reserve regions unaccessible to the driver during initialization, so add mem->reserved for collecting such regions. v2: turn into an actual intel_memory_region_reserve api Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by:
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CQ Tang authored
The lmem region needs to remove the stolen part, which should just be a case of snipping it off the end. Signed-off-by:
CQ Tang <cq.tang@intel.com> Signed-off-by:
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Matthew Auld authored
Hook up the LMEM region. Addresses will start from zero, and for CPU access we get LMEM_BAR which is just a 1:1 mapping of said region. Based on a patch from Michel Thierry. v2 by Jani: - use intel_uncore_read/intel_uncore_write - remove trailing blank line v3: s/drm_info/drm_dbg for info which in non-pertinent for the user Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Matthew Auld authored
Device local memory is very much a GT thing, therefore it should be the responsibility of the GT to setup the device local memory region. Suggested-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
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Emil Renner Berthing authored
This converts the driver to use the new tasklet API introduced in commit 12cc923f ("tasklet: Introduce new initialization API") v2: Fix up selftests/execlists. Signed-off-by:
Emil Renner Berthing <kernel@esmil.dk> Reviewed-by:
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Matthew Auld authored
The largest possible order is (63-PAGE_SHIFT), given that our min chunk size is PAGE_SIZE. With that we should only need at most 6 bits to represent all possible orders, giving us back 4 bits for other potential uses. Include a simple selftest to verify this. Signed-off-by:
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Chris Wilson authored
In defer_request() we start with the request we just unsubmitted (that should be the active request on the gpu) and then defer all of its waiters. No waiter should be ahead of the active request, so none should be marked as active. That assert failed. Of particular note this machine was undergoing persistent GPU resets due to underlying HW issues, so that may be a clue. A request is also marked as active when it is retired, regardless of current queue status, and so this assertion failure may be a result of the queue being completed by the reset and then subsequently processed by the tasklet. We can filter out retired requests here by doing the assertion check after the is-ready check (active is a subset of being ready). Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2978Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140136.10494-2-chris@chris-wilson.co.ukSigned-off-by:
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Chris Wilson authored
As we reset the engine between verifying the workarounds remain intact, report an engine reset failure. Signed-off-by:
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Matthew Auld authored
Throw it into a simple helper, and throw a warning if we encounter an object which has been initialised with an object size that exceeds our limit of INT_MAX pages. Suggested-by:
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Matthew Auld authored
At least for the time being, we need to limit our object sizes such that the number of pages can fit within a 32b signed int. It looks like we should also apply the same restriction to any imported dma-buf. Signed-off-by:
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Chris Wilson authored
Checkpatch worries that the 'return' before an else clause might be redundant. In this case, it is avoiding hitting the MISSING_CASE() warning. Let us appease checkpatch by falling through to the end of the function, which typically means that we then clean up the unused wa_list. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-10-chris@chris-wilson.co.ukSigned-off-by:
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Chris Wilson authored
Checkpatch noticed a while(0) and complains about the lack of space. Signed-off-by:
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Chris Wilson authored
Checkpatch spotted a couple of commas where we can use the more common ';', and so not worry about the subtle implications of sequence points. Signed-off-by:
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Chris Wilson authored
Checkpatch wants spaces, let's give it some spaces. Signed-off-by:
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Chris Wilson authored
Checkpatch noticed that ppgtt->pd should have been (ppgtt)->pd to avoid issues with macros. Signed-off-by:
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Chris Wilson authored
Trailing newlines before closing the function are best forgotten, or else checkpatch moans. Signed-off-by:
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Chris Wilson authored
Remember to align parameters to the '(', thanks checkpatch Signed-off-by: -
Chris Wilson authored
Checkpatch spotted a few repeated words in the comment, genuine mistakes. Signed-off-by:
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Chris Wilson authored
Trivial checkpatch cleanup. Signed-off-by:
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Chris Wilson authored
Clean up the SPDX licence declarations to comply with checkpatch. Signed-off-by:
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Tvrtko Ursulin authored
Commit 6ce1c33d ("drm/i915: Kill INTEL_SUBPLATFORM_AML") removed the only platform which used bit 2 so could also decrease the INTEL_SUBPLATFORM_BITS definition. This is not a fixes material but still lets make it precise. v2: * Fix assert in intel_device_info_subplatform_init by introducing INTEL_SUBPLATFORM_MASK. (Chris) * Update intel_subplatform(). Signed-off-by:
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Chris Wilson authored
For reasons I cannot explain, except to say this is Sandybridge after all, call stop_ring() again dring ring resume in order to prevent mysterious hard hangs. Testcase: igt/i915_selftest/hangcheck # snb Signed-off-by:
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Chris Wilson authored
As we do not have any internal priority levels, the priority can be set directed from the user values. Signed-off-by:
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Chris Wilson authored
Since we are not using any internal priority levels, and in the next few patches will introduce a new index for which the optimisation is not so lear cut, discard the small table within the priolist. Signed-off-by:
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- 17 Mar, 2021 1 commit
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Highlights: - Alderlake S enabling, via topic branch (Aditya, Anusha, Caz, José, Lucas, Matt, Tejas) - Refactor display code to shrink intel_display.c etc. (Dave) - Support more gen 9 and Tigerlake PCH combinations (Lyude, Tejas) - Add eDP MSO support (Jani) Display: - Refactor to support multiple PSR instances (Gwan-gyeong) - Link training debug logging updates (Sean) - Updates to eDP fixed mode handling (Jani) - Disable PSR2 on JSL/EHL (Edmund) - Support DDR5 and LPDDR5 for bandwidth computation (Clint, José) - Update VBT DP max link rate table (Shawn) - Disable the QSES check for HDCP2.2 over MST (Juston) - PSR updates, refactoring, selective fetch (José, Gwan-gyeong) - Display init sequence refactoring (Lucas) - Limit LSPCON to gen 9 and 10 platforms (Ankit) - Fix DDI lane polarity per VBT info (Uma) - Fix HDMI vswing programming location in mode set (Ville) - Various display improvements and refactorings and cleanups (Ville) - Clean up DDI clock routing and readout (Ville) - Workaround async flip + VT-d corruption on HSW/BDW (Ville) - SAGV watermark fixes and cleanups (Ville) - Silence pipe tracepoint WARNs (Ville) Other: - Remove require_force_probe protection from RKL, may need to be revisited (Tejas) - Detect loss of MMIO access (Matt) - GVT display improvements - drm/i915: Disable runtime power management during shutdown (Imre) - Perf/OA updates (Umesh) - Remove references to struct drm_device.pdev, via topic branch (Thomas) - Backmerge (Jani) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87v99rnk1g.fsf@intel.com
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- 16 Mar, 2021 2 commits
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https://github.com/intel/gvt-linuxJani Nikula authored
gvt-next-2021-03-16 - Parse accurate vGPU virtual display rate (Colin) - Convert vblank timer as per-vGPU based on current rate (Colin) - spelling fix (Bhaskar) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 5.13: UAPI Changes: Cross-subsystem Changes: Core Changes: - %p4cc printk format modifier - atomic: introduce drm_crtc_commit_wait, rework atomic plane state helpers to take the drm_commit_state structure - dma-buf: heaps rework to return a struct dma_buf - simple-kms: Add plate state helpers - ttm: debugfs support, removal of sysfs Driver Changes: - Convert drivers to shadow plane helpers - arc: Move to drm/tiny - ast: cursor plane reworks - gma500: Remove TTM and medfield support - mxsfb: imx8mm support - panfrost: MMU IRQ handling rework - qxl: rework to better handle resources deallocation, locking - sun4i: Add alpha properties for UI and VI layers - vc4: RPi4 CEC support - vmwgfx: doc cleanup Signed-off-by:
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- 15 Mar, 2021 3 commits
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Sean Paul authored
One instance of DRM_DEBUG_KMS was leftover in dp_link_training, convert it to the new shiny. Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Sean Paul authored
This patch adds some newlines which are missing from debug messages. This will prevent logs from being stacked up in dmesg. Signed-off-by:
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Umesh Nerlige Ramappa authored
SAMPLE_OA parameter enables sampling of OA buffer and results in a call to init the OA buffer which initializes the OA unit head/tail pointers. The OA_EXPONENT parameter controls the periodicity of the OA reports in the OA buffer and results in starting a hrtimer. Before gen12, all use cases required the use of the OA buffer and i915 enforced this setting when vetting out the parameters passed. In these platforms the hrtimer was enabled if OA_EXPONENT was passed. This worked fine since it was implied that SAMPLE_OA is always passed. With gen12, this changed. Users can use perf without enabling the OA buffer as in OAR use cases. While an OAR use case should ideally not start the hrtimer, we see that passing an OA_EXPONENT parameter will start the hrtimer even though SAMPLE_OA is not specified. This results in an uninitialized OA buffer, so the head/tail pointers used to track the buffer are zero. This itself does not fail, but if we ran a use-case that SAMPLED the OA buffer previously, then the OA_TAIL register is still pointing to an old value. When the timer callback runs, it ends up calculating a wrong/large number of available reports. Since we do a spinlock_irq_save and start processing a large number of reports, NMI watchdog fires and causes a crash. Start the timer only if SAMPLE_OA is specified. v2: - Drop SAMPLE OA check when appending samples (Ashutosh) - Prevent read if OA buffer is not being sampled Fixes: 00a7f0d7 ("drm/i915/tgl: Add perf support on TGL") Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210305210947.58751-1-umesh.nerlige.ramappa@intel.com
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- 14 Mar, 2021 1 commit
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Linus Torvalds authored
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