- 03 Jun, 2020 8 commits
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Christophe JAILLET authored
'pinctrl_unregister()' should not be called to undo 'devm_pinctrl_register_and_init()', it is already handled by the framework. This simplifies the error handling paths of the probe function. The 'imx_free_resources()' can be removed as well. Fixes: a51c158b ("pinctrl: imx: use radix trees for groups and functions") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20200530204955.588962-1-christophe.jaillet@wanadoo.frSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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yu kuai authored
A coccicheck run provided information like the following: drivers/pinctrl/sirf/pinctrl-sirf.c:798:2-8: ERROR: missing put_device; call of_find_device_by_node on line 792, but without a corresponding object release within this function. Generated by: scripts/coccinelle/free/put_device.cocci Thus add a jump target to fix the exception handling for this function implementation. Fixes: 51302162 ("PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII") Signed-off-by:
yu kuai <yukuai3@huawei.com> Link: https://lore.kernel.org/r/20200603013532.755220-1-yukuai3@huawei.comSigned-off-by:
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Christophe JAILLET authored
When 'pinctrl_register()' has been turned into 'devm_pinctrl_register()', an error handling path has not been updated. Axe a now unneeded 'pinctrl_unregister()'. Fixes: e55e025d ("pinctrl: imxl: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by:
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Florian Fainelli authored
Leverage the IRQCHIP_MASK_ON_SUSPEND flag in order to avoid having to specifically treat the GPIO interrupts during suspend and resume, and simply implement an irq_set_wake() callback that is responsible for enabling the parent wake-up interrupt as a wake-up interrupt. To avoid allocating unnecessary resources for other chips, the wake-up interrupts are only initialized if we have a brcm,bcm7211-gpio compatibility string. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20200531001101.24945-5-f.fainelli@gmail.comSigned-off-by:
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Florian Fainelli authored
The BCM7211 SoC uses the same pinconf_ops as the ones defined for the BCM2711 SoC, match the compatible string and use the correct set of options. Signed-off-by:
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Florian Fainelli authored
BCM7211 supports wake-up interrupts in the form of optional interrupt lines, one per bank, plus the "all banks" interrupt line. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200531001101.24945-3-f.fainelli@gmail.comSigned-off-by:
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Florian Fainelli authored
Document the brcm,bcm7211-gpio compatible string in the brcm,bcm2835-gpio.txt document. Signed-off-by:
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Benjamin Gaignard authored
Driver use interrupt-parent field so update the bindings to allow it. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by:
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- 25 May, 2020 3 commits
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Tiezhu Yang authored
Add COMPILE_TEST support to the AT91 PIO4 pinctrl driver for better compile testing coverage. Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Link: https://lore.kernel.org/r/1590234326-2194-2-git-send-email-yangtiezhu@loongson.cnSigned-off-by:
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Tiezhu Yang authored
When call function devm_platform_ioremap_resource(), we should use IS_ERR() to check the return value and return PTR_ERR() if failed. Fixes: 4b024225 ("pinctrl: use devm_platform_ioremap_resource() to simplify code") Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.8 (take two) - Add support for the new RZ/G1H (r8a7742) SoC, - Minor fixes and improvements.
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- 20 May, 2020 1 commit
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Geert Uytterhoeven authored
Change "PIN CONTROLLER - RENESAS" section from Maintained to Supported. This brings it in line with my other "+renesas" entries. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200518081836.23890-1-geert+renesas@glider.be
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- 19 May, 2020 1 commit
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Linus Walleij authored
Merge tag 'samsung-pinctrl-5.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.8 Two fixes for S5Pv210 pinctrl driver: setting proper external interrupt wakeup mask and restoring external interrupt mask value after system suspend.
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- 18 May, 2020 5 commits
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Lars Povlsen authored
This adds documentation for the "compatible" value designated for Sparx5 Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200513125532.24585-8-lars.povlsen@microchip.comSigned-off-by:
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Lars Povlsen authored
This fixes a problem with using the GPIO as an interrupt on Jaguar2 (and similar), as the register layout of the platforms with 64 GPIO's are pairwise, such that the original offset must be multiplied with the platform stride. Fixes: da801ab5 pinctrl: ocelot: add MSCC Jaguar2 support. Reviewed-by:
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Lars Povlsen authored
This patch removes the instance number from the "miim", "reco_clk" and "sfp" pin function. The change needed is to prepare the driver for adding new platforms with more of these instances. The instance number is also redundant, as this is implicit for each pin. Reviewed-by:
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Lars Povlsen authored
This fixes the situation where the GPIO controller is not used as an interrupt controller as well. Previously, the driver would silently fail to register even the GPIO's. With this change, the driver will only register as an interrupt controller if a parent interrupt is provided. Reviewed-by:
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Johan Jonker authored
The Rockchip dtsi and dts files have been bulk-converted for the remaining raw gpio numbers into their descriptive counterparts and also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings, so update the example as well. Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200512203524.7317-2-jbx6244@gmail.comSigned-off-by:
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- 16 May, 2020 2 commits
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Geert Uytterhoeven authored
Currently the AMD pin controller driver supports ACPI platform only. Make the PINCTRL_AMD config symbol depend on ACPI, to avoid asking the user about it when configuring a kernel without ACPI support. Signed-off-by:
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Geert Uytterhoeven authored
The Equilibrium pin controller is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PINCTRL_EQUILIBRIUM config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by:
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- 15 May, 2020 4 commits
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.8-1 * Introduce GPIO driver for Jasper Lake * Fix long standing bug in Sunrisepoint-H PAD locking code * Enable pin configuration setting for GPIO chip for Baytrail * Work around race condition in Cherriview hardware when handle IRQ * Clean up Cherryview code to be closer to other drivers The following is an automated git shortlog grouped by driver: baytrail: - Use platform_get_irq_optional() explicitly - Enable pin configuration setting for GPIO chip cannonlake: - Use generic flag for special GPIO base treatment cherryview: - Add missing spinlock usage in chv_gpio_irq_handler - Use GENMASK() consistently - Re-use data structures from pinctrl-intel.h (part 2) icelake: - Use generic flag for special GPIO base treatment intel: - Move npins closer to pin_base in struct intel_community - Update description in struct intel_community - Add Intel Jasper Lake pin controller support - Introduce new flag to force GPIO base to be 0 - Introduce common flags for GPIO mapping scheme lynxpoint: - Use platform_get_irq_optional() explicitly sunrisepoint: - Fix PAD lock register offset for SPT-H tigerlake: - Use generic flag for special GPIO base treatment
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Geert Uytterhoeven authored
rza1_swio_pin relates to the swio flag instead of the bidir flag. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20200507074516.29903-1-geert+renesas@glider.be
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Lad Prabhakar authored
Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Lad Prabhakar authored
Document PFC support for the RZ/G1H (R8A7742) SoC. Signed-off-by:
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- 12 May, 2020 5 commits
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Dafna Hirschfeld authored
In function rockchip_dt_node_to_map, a new_map variable is allocated by: new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL); This uses devres and attaches new_map to the pinctrl driver. This cause a leak since new_map is not released when the probed driver is removed. Fix it by using kcalloc to allocate new_map and free it in `rockchip_dt_free_map` Signed-off-by:
Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20200506100903.15420-1-dafna.hirschfeld@collabora.comSigned-off-by:
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Dafna Hirschfeld authored
The function rockchip_pinctrl_parse_dt returns -EINVAL if allocation fails. Change the return error to -ENOMEM Signed-off-by:
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Arnd Bergmann authored
Kbuild warns when this file is built as a loadable module: WARNING: modpost: missing MODULE_LICENSE() in drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o see include/linux/module.h for more information Add the missing license/author/description tags. Fixes: 8174a851 ("pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200505140848.554957-1-arnd@arndb.deSigned-off-by:
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Paul Cercueil authored
These are called when a GPIO is to be used as IRQ. Without these custom callbacks, when an interrupt is requested directly and not through gpiod_to_irq(), the request fails because the GPIO is not necesarily in input mode. These callbacks simply enforce that the requested GPIO is in input mode. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.netSigned-off-by:
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Rikard Falkeborn authored
Mark pin_cfg as const, allowing the compiler to put the struct in .rodata instead of .data. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200425203813.6442-1-rikard.falkeborn@gmail.comSigned-off-by:
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- 08 May, 2020 1 commit
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Linus Walleij authored
Merge tag 'sh-pfc-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.8 - Fix SWIO pins on RZ/A1L, - Add missing bindings to MAINTAINERS.
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- 28 Apr, 2020 10 commits
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Linus Walleij authored
The Hulk robot reports these build warnings: drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:899:20: warning: ‘sbag_groups’ defined but not used [-Wunused-const-variable=] DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1"); ^ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:570:23: warning: ‘ipgpio6_c_2_pins’ defined but not used [-Wunused-const-variable=] static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; ^~~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:472:23: warning: ‘mc1dir_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, ^~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:453:23: warning: ‘modem_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, ^~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:430:23: warning: ‘kpskaskb_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; ^~~~~~~~~~~~~~~~~ They are just very old bugs in seldomly used pin groups. Fix the problem by using the pins and referencing the function. Reported-by:Hulk Robot <hulkci@huawei.com> Reported-by:
Jason Yan <yanaijie@huawei.com> Signed-off-by:
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Linus Walleij authored
The Hulk robot reports an usused varible: drivers/pinctrl/nomadik/pinctrl-ab8505.c:137:23: warning: ‘gpio50_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; ^~~~~~~~~~~~~~~ This variable actually should be used. Probably an oversight by the driver author. Cc: Patrice Chotard <patrice.chotard@st.com> Reported-by: -
Jason Yan authored
The 'pwm37' is not added to bm1880_pctrl_groups, which triggers a gcc build warning: drivers/pinctrl/pinctrl-bm1880.c:263:27: warning: ‘pwm37_pins’ defined but not used [-Wunused-const-variable=] static const unsigned int pwm37_pins[] = { 110 }; Signed-off-by:Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200428115543.33379-1-yanaijie@huawei.comSigned-off-by:
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Amelie Delaunay authored
Pin direction is not used to set pin configuration. Fixes: a502b343 ("pinctrl: stmfx: update pinconf settings") Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20200422072513.8352-1-amelie.delaunay@st.comSigned-off-by:
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Dejin Zheng authored
use codespell to fix lots of typos over frontends. Signed-off-by:
Dejin Zheng <zhengdejin5@gmail.com> Reviewed-by:
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Martin Blumenstingl authored
Use gpiochip_generic_config for the gpio_chip's set_config callback so GPIO flags like GPIO_PULL_UP or GPIO_PULL_DOWN can be used in the board .dts descriptions. This is required for some Meson8m2 boards where GPIO_BSD_EN provides the "MUTE" signal and requires enabling the internal pull-up resistor. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20200417183349.1283092-3-martin.blumenstingl@googlemail.comSigned-off-by:
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Martin Blumenstingl authored
Implement the get_direction callback so we read the direction from the actual GPIO controller register. This is recommended by the gpio_chip kernel doc. Signed-off-by:
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Jonathan Bakker authored
Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers are saved and restored over a suspend/resume cycle. However, the EINT_MASK registers are not. On S5PV210 at the very least, these registers are not retained over suspend, leading to the interrupts remaining masked upon resume and therefore no interrupts being triggered for the device. There should be no effect on any SoCs that do retain these registers as theoretically we would just be re-writing what was already there. Fixes: 7ccbc60c ("pinctrl: exynos: Handle suspend/resume of GPIO EINT registers") Cc: <stable@vger.kernel.org> Signed-off-by:
Jonathan Bakker <xc-racer2@live.ca> Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org>
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Venkata Narendra Kumar Gutta authored
Add initial Qualcomm SM8250 pinctrl driver to support pin configuration with pinctrl framework for SM8250 SoC. Signed-off-by:
Rishabh Bhatnagar <rishabhb@codeaurora.org> Signed-off-by:
Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Link: https://lore.kernel.org/r/1586477057-7636-2-git-send-email-vnkgutta@codeaurora.org [bjorn: Regrouped functions, upstream tiles implementation, dropped downstream-only features] Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200417061907.1226490-3-bjorn.andersson@linaro.orgSigned-off-by:
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Bjorn Andersson authored
Add device tree binding Documentation details for Qualcomm SM8250 pinctrl driver. Signed-off-by:
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