- 09 May, 2022 10 commits
-
-
Marc Kleine-Budde authored
In mx51_ecspi_prepare_message() the MX51_ECSPI_CONFIG register is setup for the current spi_message. After writing the register, there is a delay to ensure that the changes hit the hardware. This patch checks if the register MX51_ECSPI_CONFIG actually needs to be changed. If the register content is unchanged the function is left early, skipping the write to the hardware and the delay. This leads to a small, but measurable performance increase. For a given workload with small transfers on an imx6 single core the CPU load decreases from 30% to ~27%. Signed-off-by:
Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220502175457.1977983-10-mkl@pengutronix.deSigned-off-by:
Mark Brown <broonie@kernel.org>
-
Marc Kleine-Budde authored
The driver supports several modes, one of them is PIO/IRQ "spi_imx_pio_transfer()". The data is exchanged with the IP core using PIO, an IRQ is setup to signal empty/full FIFOs and the end of the transfer. The IRQ and scheduling overhead for short transfers is significant. Using polling instead of IRQs can be beneficial to reduce the overall CPU load, especially on small transfer workloads. On an imx6 single core, a given RX workload of the mcp251xfd driver results in 40% CPU load. Using polling mode reduces the CPU load to 30%. This patch adds PIO polling support to the driver. For transfers with a duration of less than 30 µs the polling mode instead of IRQ based PIO mode is used. 30 µs seems to be a good compromise, which is used the by the SPI drivers for the raspberry Pi (spi-bcm2835, spi-bcm2835), too. Co-developed-by:
David Jander <david@protonic.nl> Signed-off-by:
-
Marc Kleine-Budde authored
There's no need to embed the struct spi_bitbang into our private data (struct spi_imx_data), the spi core is flexible enough, so that we only need a pointer to the allocated struct spi_controller. This is also a preparation patch to add PIO based polling support to the driver. Co-developed-by:
-
Marc Kleine-Budde authored
With patch: | 8caab75f ("spi: Generalize SPI "master" to "controller"") the SPI "master" was generalized to "controller". This patch completed the conversion of the spi-imx driver by replacing the remaining occurrences of master to controller. Signed-off-by:
-
Marc Kleine-Budde authored
This patch replaces an open coded swahw32s(). Signed-off-by:
-
Marc Kleine-Budde authored
This patch fixes the following sparse warning by using a swab32s() instead of a cpu_to_be32(). The driver is used on little endian systems only and we really want to swap the bytes. | drivers/spi/spi-imx.c:305:29: warning: incorrect type in assignment (different base types) | drivers/spi/spi-imx.c:305:29: expected unsigned int val | drivers/spi/spi-imx.c:305:29: got restricted __be32 [usertype] | drivers/spi/spi-imx.c:361:21: warning: incorrect type in assignment (different base types) | drivers/spi/spi-imx.c:361:21: expected unsigned int [assigned] [usertype] val | drivers/spi/spi-imx.c:361:21: got restricted __be32 [usertype] Signed-off-by:
-
Marc Kleine-Budde authored
This patch fixes the following checkpatch warning, by making val an "unsigned int". | WARNING: Prefer 'unsigned int' to bare use of 'unsigned' | + unsigned val = 0; Signed-off-by:
-
Marc Kleine-Budde authored
This patch fixes the following checkpatch warning by removing the trailing backslash: | WARNING: Avoid unnecessary line continuations | + spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ Signed-off-by:
-
Marc Kleine-Budde authored
This patch fixes the following and similar sparse warnings by adding the missing identifier names to the function definitions: | WARNING: function definition argument 'struct spi_imx_data *' should also have an identifier name | #68: FILE: drivers/spi/spi-imx.c:68: | + int (*prepare_message)(struct spi_imx_data *, struct spi_message *); Signed-off-by:
-
Yang Yingliang authored
It will cause null-ptr-deref if platform_get_resource_byname() returns NULL, we need check the return value. Fixes: 858e26a5 ("spi: spi-fsl-qspi: Reduce devm_ioremap size to 4 times AHB buffer size") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220505093954.1285615-1-yangyingliang@huawei.comSigned-off-by:
-
- 04 May, 2022 1 commit
-
-
Andrea Zanotti authored
The module omap2-mcspi does not support the interword delay parameter present in the spi transfer. On one side, if the module is instructed to use the dma, this parameter is correctly ignored. However, without the usage of the dma, that parameter should be used. The patch introduce the handling of such delay in the omap2-mcspi module, using standard spi_delay struct. The patch has been tested using as benchmark a DM3730. The delay function used (spi_delay_exec) is already present in the kernel and it checks on its own the validity of the input, as such, no additional checks are present. The range of usage of the udelay function is incremented to 200 us, as the change from udelay to usleep_range introduces not neglectible delays. Signed-off-by:
Andrea Zanotti <andreazanottifo@gmail.com> Link: https://lore.kernel.org/r/20220502111300.24754-1-andreazanottifo@gmail.comSigned-off-by:
-
- 03 May, 2022 2 commits
-
-
Biju Das authored
Add RSPI binding documentation for Renesas RZ/G2UL SoC. RSPI block is identical to one found on RZ/A, so no driver changes are required. The fallback compatible string "renesas,rspi-rz" will be used on RZ/G2UL. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220501082150.24662-1-biju.das.jz@bp.renesas.comSigned-off-by:
-
Dan Carpenter authored
Return -ENOMEM of there is a dma mapping error. Do not return success. Fixes: 764f1b74 ("spi: add driver for MTK SPI NAND Flash Interface") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/YmwjUcTKyQNrrn2g@kiliSigned-off-by:
-
- 27 Apr, 2022 5 commits
-
-
Chuanhong Guo authored
Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by:
-
Chuanhong Guo authored
This driver implements support for the SPI-NAND mode of MTK NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.comSigned-off-by:
-
Mark Brown authored
Mediatek ECC changes: * Also parse the default nand-ecc-engine property if available * Make mtk_ecc.c a separated module needed for SPI controller driver
-
Chuanhong Guo authored
The recently added ECC engine support introduced a generic property named nand-ecc-engine for ecc engine phandle. This patch adds support for this new property. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220424032527.673605-4-gch981213@gmail.com
-
Chuanhong Guo authored
this code will be used in mediatek snfi spi-mem controller with pipelined ECC engine. Signed-off-by:
-
- 25 Apr, 2022 16 commits
-
-
Mark Brown authored
Merge series from 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>: 1.Add support for using GPIOs as chip select lines on Ingenic SoCs. 2.Add support for probing the spi-ingenic driver on the JZ4775 SoC, the X1000 SoC, and the X2000 SoC. 3.Modify annotation texts to be more in line with the current state.
-
Alexander Shiyan authored
Since version 5.13, the standard syscon bindings have been added to all clps711x DT nodes, so we can now use the more general syscon_regmap_lookup_by_phandle function to get the syscon pointer. Signed-off-by:
Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.kernel.org/r/20220420061038.22570-1-eagle.alexander923@gmail.comSigned-off-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220420090452.2588930-1-chi.minghao@zte.com.cnSigned-off-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
-
Matthias Schiffer authored
With the removal of the incorrect logic of cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previously allowed 8-8-8 ops). Signed-off-by:
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.comSigned-off-by:
-
Matthias Schiffer authored
As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
-
Luca Ceresoli authored
The hardware (except for the ROCKCHIP_SPI_VER2_TYPE2 version) does not support active-high native chip selects. However if such a CS is configured the core does not error as it normally should, because the 'ctlr->use_gpio_descriptors = true' line in rockchip_spi_probe() makes the core set SPI_CS_HIGH in ctlr->mode_bits. In such a case the spi-rockchip driver operates normally but produces an active-low chip select signal without notice. There is no provision in the current core code to handle this situation. Fix by adding a check in the ctlr->setup function (similarly to what spi-atmel.c does). This cannot be done reading the SPI_CS_HIGH but in ctlr->mode_bits because that bit gets always set by the core for master mode (see above). Fixes: eb1262e3 ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods") Signed-off-by:
Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://lore.kernel.org/r/20220421213251.1077899-1-luca.ceresoli@bootlin.comSigned-off-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
-
Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
-
周琰杰 (Zhou Yanjie) authored
1.Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4775-spi" compatible string in the driver. This will permit to support the JZ4775 by having: compatible = "ingenic,jz4775-spi"; Instead of doing: compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi"; 2.Add support for probing the spi-ingenic driver on the X1000 SoC from Ingenic. From the X1000 SoC onwards, the maximum frequency allowed by the SSI module of Ingenic SoCs has been changed from 54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info" to set different maximum frequency values. 3.Add support for probing the spi-ingenic driver on the X2000 SoC from Ingenic. The X2000 SoC has only one native chip select line, so "max_native_cs" is introduced in "jz_soc_info" to set different maximum number of native chip select lines. 4.Because of the introduction of support for the X-series SoCs, the current driver is not only applicable to the JZ-series SoCs, so the description texts has been modified to avoid misunderstanding. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add the SPI bindings for the JZ4775 SoC, the X1000 SoC, and the X2000 SoC from Ingenic. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add support for using GPIOs as chip select lines on Ingenic SoCs. Signed-off-by:
-
- 22 Apr, 2022 1 commit
-
-
Zheng Yongjun authored
If the device is already in a runtime PM enabled state pm_runtime_get_sync() will return 1, so a test for negative value should be used to check for errors. Fixes: deba2580 ("spi: Add driver for IMG SPFI controller") Signed-off-by:
Zheng Yongjun <zhengyongjun3@huawei.com> Link: https://lore.kernel.org/r/20220422062641.10486-1-zhengyongjun3@huawei.comSigned-off-by:
-
- 20 Apr, 2022 2 commits
-
-
Mika Westerberg authored
Currently the driver goes over the supported opcodes list each time ->exec_op() is called and finds the suitable for the given operation. This consumes unnecessary amount of CPU cycles because the operation is always the same. For this reason populate dirmap hooks for the driver so that we cache the selected operation and then simply call it on each read/write. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220420104350.19510-1-mika.westerberg@linux.intel.comSigned-off-by:
-
Mark Brown authored
Merge series from AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>: This series performs some cleanups to the spi-mt65xx driver, removing all gotos, simplifying the probe function and adding kerneldoc to the driver structures.
-
- 19 Apr, 2022 3 commits
-
-
AngeloGioacchino Del Regno authored
Some definitions at the beginning of this file were wrongly indented: fix the indentation for all of these and, while at it, also move the MTK_SPI_IDLE and MTK_SPI_PAUSED down, as to implicitly group the hardware related definitions to the software (driver) related ones. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220407114428.167091-9-angelogioacchino.delregno@collabora.comSigned-off-by:
-
AngeloGioacchino Del Regno authored
One of the two structures was already partially documented, but not in kerneldoc format: enhance readability by adding the missing documentation bits and use kerneldoc. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Switch to dev_err_probe() to remove all dev_err() -> return repeated patterns, simplifying and shortening the probe function. Signed-off-by:
-
