- 26 Sep, 2017 40 commits
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Harry Wentland authored
DCN code for display interrupts. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Implement support for i2c and aux on DCN. Signed-off-by:
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Harry Wentland authored
GPIOs are used for i2c and other things. Signed-off-by:
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Harry Wentland authored
Display mode lib handles clock, watermark, and bandwidth calculations for DCN. Signed-off-by:
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Harry Wentland authored
Core display support for DCN. Signed-off-by:
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Harry Wentland authored
Bandwidth and scaling calculations for DCN. Signed-off-by:
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Arindam Nath authored
There is a hard hang observed during resume from S3 when the system receives a DP short pulse interrupt. This is because there are two code paths contending for GPIO access for AUX channel transactions. One such path is through amdgpu_dm_display_resume() function which is invoked from the regular system resume code path. The other path is through handle_hpd_rx_irq(), which is invoked in response to system receiving DP short pulse interrupt. handle_hpd_rx_irq() guards against conflicting GPIO access using hpd_lock, but the GPIO access from amdgpu_dm_display_resume() remains unguarded. This patch makes sure we use hpd_lock inside amdgpu_dm_display_resume() to avoid race conditions for GPIO access. Signed-off-by:
Arindam Nath <arindam.nath@amd.com> Signed-off-by:
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Harry Wentland authored
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Hersen Wu authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Tony Cheng authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Eric Cook authored
Signed-off-by:
Eric <eric.cook@amd.com> Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Ding Wang authored
Signed-off-by:
Ding Wang <Ding.Wang@amd.com> Acked-by:
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Eric Cook authored
-check for min/max range in freesync calculation and handle it accordingly Signed-off-by:
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Dmytro Laktyushkin authored
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Ding Wang authored
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Tony Cheng authored
to avoid null access in case res_ctx is used to access res_pool before it's fully constructed also make it clear which function has dependency on resource_pool Signed-off-by:
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Eric Cook authored
Implement core support to allow for FreeSync Auto Sweep to work Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Tony Cheng authored
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Sylvia Tsai authored
- Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by:
Sylvia Tsai <sylvia.tsai@amd.com> Acked-by:
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Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Yongqiang Sun authored
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Amy Zhang authored
Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
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Zeyu Fan authored
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Shirish S authored
dc_commit_surfaces_to_stream() function currently is handle's only one plane at a time. This will not work if multiple planes have to be set to a crtc. The functionality of dc_commit_surfaces_to_stream() with this patch is slit into 1. Accumulate and initialise all the surfaces that needs to be set to a crtc. 2. Update the intialised set of surfaces to the steam in one go. Hence dc_commit_surfaces_to_stream() is renamed to init_surfaces(). Once all the planes requested by user space are initialised, dc_commit_surfaces_to_stream() shall sequentially populates *updates, *flip_addr, *plane_info and *scaling_info for all surfaces. BUG: SWDEV-119421 TEST: (On Chromium OS for Stoney Only) * Chromium UI comes up, on both eDP & DP. * 'new_surface_count' now changes as per user input for e.g for all below run tests its 2, without this patch for the below tests it used to be 1 * Executed below tests to see YUV(underlay) & RGB planes on eDP plane_test --format XR24 --size 500x100 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 150x150 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Shirish S authored
This patch updates the planes default offsets to the appropriate ones, and aligns the pitch to 64 bits. BUG=SWDEV-119421 TEST=Boots to UI on jadeite TEST= plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1280x720 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by: -
Shirish S authored
This patch populates the YUV surface configurations. Tests: (On Chromium OS for Stoney Only) builds without any errors. Signed-off-by:
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Harry Wentland authored
This will allow us to carry it from check to commit Signed-off-by:
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Harry Wentland authored
This will be needed to clean up context once we add it to private atomic state. Signed-off-by:
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Harry Wentland authored
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