- 04 Apr, 2013 10 commits
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Sylwester Nawrocki authored
This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Thomas Abraham <thomas.abraham@linaro.org> Acked-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Tomasz Figa authored
This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by:
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Tomasz Figa authored
Unimplemented clock operations should be simply omitted instead of returning error values. This patch removes unimplemented PLL operations to fix problems caused by returning error code in round_rate callback. Signed-off-by:
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Lukasz Majewski authored
This patch exports clocks used by Exynos cpufreq drivers to allow lookup using device tree. (Support to cpufreq drivers will be added in further patches.) Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com> Signed-off-by:
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Tomasz Figa authored
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12. Signed-off-by:
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Tomasz Figa authored
This clock is used by PCM interface 0. Signed-off-by:
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Tomasz Figa authored
This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by:
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Tomasz Figa authored
This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by:
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Tomasz Figa authored
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by:
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Sylwester Nawrocki authored
This clock must be exported to allow lookup using device tree. Signed-off-by:
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- 28 Mar, 2013 4 commits
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Heiko Stuebner authored
The current code adds aliases, if necessary, directly when adding the clock, limiting the number of possible aliases to one. Some platforms need more than one alias, like the hsmmc pclocks on s3c2416 which need a "hsmmc" and "mmc_busclk.0" alias for the s3c- sdhci driver. Therefore add the possibility to separately add clock aliases for previously created clocks. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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Heiko Stuebner authored
This is needed to allow looking up previous created clocks when adding separate aliases to them. Signed-off-by:
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Heiko Stueber authored
The clock_init function checked for a dt node, returning immediately for non-dt machines. This let to the suspend init never being reached on those non-DT machines. So fix this by moving the pm init code above the check. Signed-off-by:
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Heiko Stuebner authored
On some Samsung platforms divider clocks only use specific divider combinations like the armdiv on s3c2443 and s3c2416. For these usecases the generic divider clock already provides the option of providing a lookup table mapping register values to divider values. Therefore add a new field to samsung_div_clock and if filled with a table, use clk_register_divider_table instead of clk_register_divider to register a divider clock Signed-off-by:
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- 25 Mar, 2013 16 commits
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Thomas Abraham authored
The clock frequency of xxti and xusbxti clocks is dependent on the frequency of the on-board oscillator that is used to generate these clocks. So allow the frequency of these clocks to be specfied from device tree. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos5440, add clock lookup information. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos5250, add clock lookup information. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos4 SoCs, add clock lookup information. Reviewed-by:
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Thomas Abraham authored
Add clock controller nodes for EXYNOS4210, EXYNOS4x12, EXYNOS5250 and EXYNOS5440 SoCs. Signed-off-by:
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Thomas Abraham authored
Add support for mct clock lookup and setup to ensure that the mct clock is has been turned on. Signed-off-by:
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Thomas Abraham authored
With the migration of Exynos4 clocks to use common clock framework, the old styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used as the tick clock for mct controller. Signed-off-by:
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Thomas Abraham authored
With support for device tree based clock lookup now available, remove the auxdata table from exynos4/5 dt-enabled machine file. Signed-off-by:
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Thomas Abraham authored
The clock speed of xxti and xusbxti clocks depends on the oscillator used on the board to generate these clocks. For non-dt platforms, allow the board support for those platforms to set the clock frequency of xxti and xusbxti clocks. Signed-off-by:
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Thomas Abraham authored
Since the clock initialization should be completed prior to the mct timer initialization, create a new function 'exynos_init_time' that first sets up the clock and then invokes the timer initialization function. The 'init_time' callback in the board files are updated to invoke this new wrapper function. Signed-off-by:
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Thomas Abraham authored
Remove Samsung specific clock support in Exynos4/5 and migrate to use common clock framework. Reviewed-by:
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Thomas Abraham authored
The Exynos5440 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by:
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Thomas Abraham authored
The Exynos5250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Signed-off-by:
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Thomas Abraham authored
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by:
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Thomas Abraham authored
There are several types of pll clocks used in Samsung SoC's and these pll clocks can be represented as Samsung specific pll clock types and registered with the common clock framework. Add support for pll35xx, pll36xx, pll45xx, pll46xx and pll2550x clock types and helper functions to register them. Reviewed-by:
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Thomas Abraham authored
All Samsung platforms include different types of clock including fixed-rate, mux, divider and gate clock types. There are typically hundreds of such clocks on each of the Samsung platforms. To enable Samsung platforms to register these clocks using the common clock framework, a bunch of utility functions are introduced here which simplify the clock registration process. The clocks are usually statically instantiated and registered with common clock framework. Reviewed-by:
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- 09 Mar, 2013 9 commits
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Kukjin Kim authored
Conflicts: arch/arm/mach-exynos/mach-exynos4-dt.c
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Kukjin Kim authored
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Thomas Abraham authored
Move the multi core timer (mct) driver to from mach-exynos to drivers/clocksource and update the Kconfig and makefiles. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Thomas Abraham authored
With device tree support enabled for MCT controller, the staticio-remapping of the MCT controller address space is removed for Exynos5 platforms (which supports only device tree based boot). Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Thomas Abraham authored
Add MCT device tree node for Exynos4210, Exynos4212, Exynos4412 and Exynos5250. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Thomas Abraham authored
Add entries to __clksrc_of_table so that Exynos MCT controller is discoverable using call to clocksource_of_init. With this change, it would be appropriate to rename the function 'exynos4_timer_init' as 'mct_init' since it aptly describes this function. Additionally, the 'init_time' callback of all machine descriptors for exynos platforms that were previously set to 'exynos4_timer_init' are now set to either 'mct_init' or 'clocksource_of_init'. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Thomas Abraham authored
Allow the MCT controller base address and interrupts to be obtained from device tree and remove unused static definitions of these. The non-dt support for Exynos5250 is removed but retained for Exynos4210 based platforms. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Thomas Abraham authored
Instead of using soc_is_xxx macro at more than one place in the MCT controller driver to decide the MCT interrpt number to be setup, populate a table of known MCT global and local timer interrupts and use the values in table to setup the MCT interrupts. This also helps in adding device tree support for MCT controller driver by allowing the driver to retrieve interrupt numbers from device tree and populating them into this table, thereby supporting both legacy and dt functionality to co-exist. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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Thomas Abraham authored
All the MCT register read/writes use a fixed remapped address S5P_VA_SYSTIMER. With device tree support for MCT controller, it is possible to remove the static remap of the MCT controller address space and do the remap during the initialization of the MCT controller with the physical address obtained from the device tree. So in preparation of adding device tree support for MCT controller, add a new register base address variable that will hold the remapped MCT controller base address and convert all MCT register read/writes to use this new variable as the base address instead of the fixed S5P_VA_SYSTIMER. While at it, the MCT register offset and bit mask definitions are moved into the MCT controller driver file since there are no other consumers of these definitions. Cc: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by:
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- 07 Mar, 2013 1 commit
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Abhilash Kesavan authored
The exynos5250 based chromebooks have a max77686 pmic on i2c channel 0. Add support for the pmic in the common cros5250 dts file. Tested after enabling cpufreq support for exynos5250 SoC and varying the arm frequency/voltage using the userspace governer. Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
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