1. 25 Mar, 2020 18 commits
  2. 24 Mar, 2020 22 commits
    • Jakub Kicinski's avatar
      devlink: expand the devlink-info documentation · cd556e40
      Jakub Kicinski authored
      We are having multiple review cycles with all vendors trying
      to implement devlink-info. Let's expand the documentation with
      more information about what's implemented and motivation behind
      this interface in an attempt to make the implementations easier.
      
      Describe what each info section is supposed to contain, and make
      some references to other HW interfaces (PCI caps).
      
      Document how firmware management is expected to look, to make
      it clear how devlink-info and devlink-flash work in concert.
      
      Name some future work.
      
      v2: - improve wording
      v3: - improve wording
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      Reviewed-by: default avatarRandy Dunlap <rdunlap@infradead.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cd556e40
    • Vladimir Oltean's avatar
      net: phy: mscc: consolidate a common RGMII delay implementation · 2283a02b
      Vladimir Oltean authored
      It looks like the VSC8584 PHY driver is rolling its own RGMII delay
      configuration code, despite the fact that the logic is mostly the same.
      
      In fact only the register layout and position for the RGMII controls has
      changed. So we need to adapt and parameterize the PHY-dependent bit
      fields when calling the new generic function.
      Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Tested-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2283a02b
    • David S. Miller's avatar
      Merge branch 'axienet-Update-error-handling-and-add-64-bit-DMA-support' · 148aa2a8
      David S. Miller authored
      Andre Przywara says:
      
      ====================
      net: axienet: Update error handling and add 64-bit DMA support
      
      a minor update, fixing the 32-bit build breakage, and brightening up
      Dave's christmas tree. Rebased against latest net-next/master.
      
      This series is based on net-next as of today (9970de8b), which
      includes Russell's fixes [1], solving the SGMII issues I have had.
      
      [1] https://lore.kernel.org/netdev/E1j6trA-0003GY-N1@rmk-PC.armlinux.org.uk/
      
      Changelog v2 .. v3:
      - Use two "left-shifts by 16" to fix builds with 32-bit phys_addr_t
      - reorder variable declarations
      
      Changelog v1 .. v2:
      - Add Reviewed-by: tags from Radhey
      - Extend kerndoc documentation
      - Convert DMA error handler tasklet to work queue
      - log DMA mapping errors
      - mark DMA mapping error checks as unlikely (in "hot" paths)
      - return NETDEV_TX_OK on TX DMA mapping error (increasing TX drop counter)
      - Request eth IRQ as an optional IRQ
      - Remove no longer needed MDIO IRQ register names
      - Drop DT propery check for address width, assume full 64 bit
      
      This series updates the Xilinx Axienet driver to work on our board
      here. One big issue was broken SGMII support, which Russell fixed already
      (in net-next).
      While debugging and understanding the driver, I found several problems
      in the error handling and cleanup paths, which patches 2-7 address.
      Patch 8 removes a annoying error message, patch 9 paves the way for newer
      revisions of the IP. The next patch adds mii-tool support, just for good
      measure.
      
      The next four patches add support for 64-bit DMA. This is an integration
      option on newer IP revisions (>= v7.1), and expects MSB bits in formerly
      reserved registers. Without writing to those MSB registers, the state
      machine won't trigger, so it's mandatory to access them, even if they
      are zero. Patches 11 and 12 prepare the code by adding accessors, to
      wrap this properly and keep it working on older IP revisions.
      Patch 13 enables access to the MSB registers, by trying to write a
      non-zero value to them and checking if that sticks. Older IP revisions
      always read those registers as zero.
      Patch 14 then adjusts the DMA mask, based on the autodetected MSB
      feature. It uses the full 64 bits in this case, the rest of the system
      (actual physical addresses in use) should provide a natural limit if the
      chip has connected fewer address lines. If not, the parent DT node can
      use a dma-range property.
      
      The Xilinx PG138 and PG021 documents (in versions 7.1 in both cases)
      were used for this series.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      148aa2a8
    • Andre Przywara's avatar
      net: axienet: Allow DMA to beyond 4GB · 5fff0151
      Andre Przywara authored
      With all DMA address accesses wrapped, we can actually support 64-bit
      DMA if this option was chosen at IP integration time.
      If the IP has been configured for an address width greater than 32 bits,
      we assume the full 64 bit DMA width is working. In practise this will be
      limited by the actual system address bus width, which will ideally be the
      same as the DMA IP address width.
      If this is not the case, the actual width can still be configured using a
      dma-ranges property in the parent of the MAC node.
      
      This increases the DMA mask on those systems to let the kernel choose
      buffers from memory at higher addresses.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5fff0151
    • Andre Przywara's avatar
      net: axienet: Autodetect 64-bit DMA capability · f735c40e
      Andre Przywara authored
      When newer revisions of the Axienet IP are configured for a 64-bit bus,
      we *need* to write to the MSB part of the an address registers,
      otherwise the IP won't recognise this as a DMA start condition.
      This is even true when the actual DMA address comes from the lower 4 GB.
      
      To autodetect this configuration, at probe time we write all 1's to such
      an MSB register, and see if any bits stick. If this is configured for a
      32-bit bus, those MSB registers are RES0, so reading back 0 indicates
      that no MSB writes are necessary.
      On the other hands reading anything other than 0 indicated the need to
      write the MSB registers, so we set the respective flag.
      
      The actual DMA mask stays at 32-bit for now. To help bisecting, a
      separate patch will enable allocations from higher addresses.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f735c40e
    • Andre Przywara's avatar
      net: axienet: Upgrade descriptors to hold 64-bit addresses · 4e958f33
      Andre Przywara authored
      Newer revisions of the AXI DMA IP (>= v7.1) support 64-bit addresses,
      both for the descriptors itself, as well as for the buffers they are
      pointing to.
      This is realised by adding "MSB" words for the next and phys pointer
      right behind the existing address word, now named "LSB". These MSB words
      live in formerly reserved areas of the descriptor.
      
      If the hardware supports it, write both words when setting an address.
      The buffer address is handled by two wrapper functions, the two
      occasions where we set the next pointers are open coded.
      
      For now this is guarded by a flag which we don't set yet.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4e958f33
    • Andre Przywara's avatar
      net: axienet: Wrap DMA pointer writes to prepare for 64 bit · 6a00d0dd
      Andre Przywara authored
      Newer versions of the Xilink DMA IP support busses with more than 32
      address bits, by introducing an MSB word for the registers holding DMA
      pointers (tail/current, RX/TX descriptor addresses).
      On IP configured for more than 32 bits, it is also *required* to write
      both words, to let the IP recognise this as a start condition for an
      MM2S request, for instance.
      
      Wrap the DMA pointer writes with a separate function, to add this
      functionality later. For now we stick to the lower 32 bits.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6a00d0dd
    • Andre Przywara's avatar
      net: axienet: Add mii-tool support · 2a9b65ea
      Andre Przywara authored
      mii-tool is useful for debugging, and all it requires to work is to wire
      up the ioctl ops function pointer.
      Add this to the axienet driver to enable mii-tool.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2a9b65ea
    • Andre Przywara's avatar
      net: axienet: Drop MDIO interrupt registers from ethtools dump · c30cb8f0
      Andre Przywara authored
      Newer revisions of the IP don't have these registers. Since we don't
      really use them, just drop them from the ethtools dump.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c30cb8f0
    • Andre Przywara's avatar
      net: axienet: Mark eth_irq as optional · d6349e3e
      Andre Przywara authored
      According to the DT binding, the Ethernet core interrupt is optional.
      
      Use platform_get_irq_optional() to avoid the error message when the
      IRQ is not specified.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d6349e3e
    • Andre Przywara's avatar
      net: axienet: Check for DMA mapping errors · 71791dc8
      Andre Przywara authored
      Especially with the default 32-bit DMA mask, DMA buffers are a limited
      resource, so their allocation can fail.
      So as the DMA API documentation requires, add error checking code after
      dma_map_single() calls to catch the case where we run out of "low" memory.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      71791dc8
    • Andre Przywara's avatar
      net: axienet: Factor out TX descriptor chain cleanup · ab365c33
      Andre Przywara authored
      Factor out the code that cleans up a number of connected TX descriptors,
      as we will need it to properly roll back a failed _xmit() call.
      There are subtle differences between cleaning up a successfully sent
      chain (unknown number of involved descriptors, total data size needed)
      and a chain that was about to set up (number of descriptors known), so
      cater for those variations with some extra parameters.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ab365c33
    • Andre Przywara's avatar
      net: axienet: Improve DMA error handling · e7fea0b9
      Andre Przywara authored
      Since 0 is a valid DMA address, we cannot use the physical address to
      check whether a TX descriptor is valid and is holding a DMA mapping.
      
      Use the "cntrl" member of the descriptor to make this decision, as it
      contains at least the length of the buffer, so 0 points to an
      uninitialised buffer.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e7fea0b9
    • Andre Przywara's avatar
      net: axienet: Fix DMA descriptor cleanup path · f26667a3
      Andre Przywara authored
      When axienet_dma_bd_init() bails out during the initialisation process,
      it might do so with parts of the structure already allocated and
      initialised, while other parts have not been touched yet. Before
      returning in this case, we call axienet_dma_bd_release(), which does not
      take care of this corner case.
      This is most obvious by the first loop happily dereferencing
      lp->rx_bd_v, which we actually check to be non NULL *afterwards*.
      
      Make sure we only unmap or free already allocated structures, by:
      - directly returning with -ENOMEM if nothing has been allocated at all
      - checking for lp->rx_bd_v to be non-NULL *before* using it
      - only unmapping allocated DMA RX regions
      
      This avoids NULL pointer dereferences when initialisation fails.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f26667a3
    • Andre Przywara's avatar
      net: axienet: Propagate failure of DMA descriptor setup · ee44d0b7
      Andre Przywara authored
      When we fail allocating the DMA buffers in axienet_dma_bd_init(), we
      report this error, but carry on with initialisation nevertheless.
      
      This leads to a kernel panic when the driver later wants to send a
      packet, as it uses uninitialised data structures.
      
      Make the axienet_device_reset() routine return an error value, as it
      contains the DMA buffer initialisation. Make sure we propagate the error
      up the chain and eventually fail the driver initialisation, to avoid
      relying on non-initialised buffers.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ee44d0b7
    • Andre Przywara's avatar
      net: axienet: Convert DMA error handler to a work queue · 24201a64
      Andre Przywara authored
      The DMA error handler routine is currently a tasklet, scheduled to run
      after the DMA error IRQ was handled.
      However it needs to take the MDIO mutex, which is not allowed to do in a
      tasklet. A kernel (with debug options) complains consequently:
      [  614.050361] net eth0: DMA Tx error 0x174019
      [  614.064002] net eth0: Current BD is at: 0x8f84aa0ce
      [  614.080195] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:935
      [  614.109484] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 40, name: kworker/u4:4
      [  614.135428] 3 locks held by kworker/u4:4/40:
      [  614.149075]  #0: ffff000879863328 ((wq_completion)rpciod){....}, at: process_one_work+0x1f0/0x6a8
      [  614.177528]  #1: ffff80001251bdf8 ((work_completion)(&task->u.tk_work)){....}, at: process_one_work+0x1f0/0x6a8
      [  614.209033]  #2: ffff0008784e0110 (sk_lock-AF_INET-RPC){....}, at: tcp_sendmsg+0x24/0x58
      [  614.235429] CPU: 0 PID: 40 Comm: kworker/u4:4 Not tainted 5.6.0-rc3-00926-g4a165a9d5921 #26
      [  614.260854] Hardware name: ARM Test FPGA (DT)
      [  614.274734] Workqueue: rpciod rpc_async_schedule
      [  614.289022] Call trace:
      [  614.296871]  dump_backtrace+0x0/0x1a0
      [  614.308311]  show_stack+0x14/0x20
      [  614.318751]  dump_stack+0xbc/0x100
      [  614.329403]  ___might_sleep+0xf0/0x140
      [  614.341018]  __might_sleep+0x4c/0x80
      [  614.352201]  __mutex_lock+0x5c/0x8a8
      [  614.363348]  mutex_lock_nested+0x1c/0x28
      [  614.375654]  axienet_dma_err_handler+0x38/0x388
      [  614.389999]  tasklet_action_common.isra.15+0x160/0x1a8
      [  614.405894]  tasklet_action+0x24/0x30
      [  614.417297]  efi_header_end+0xe0/0x494
      [  614.429020]  irq_exit+0xd0/0xd8
      [  614.439047]  __handle_domain_irq+0x60/0xb0
      [  614.451877]  gic_handle_irq+0xdc/0x2d0
      [  614.463486]  el1_irq+0xcc/0x180
      [  614.473451]  __tcp_transmit_skb+0x41c/0xb58
      [  614.486513]  tcp_write_xmit+0x224/0x10a0
      [  614.498792]  __tcp_push_pending_frames+0x38/0xc8
      [  614.513126]  tcp_rcv_established+0x41c/0x820
      [  614.526301]  tcp_v4_do_rcv+0x8c/0x218
      [  614.537784]  __release_sock+0x5c/0x108
      [  614.549466]  release_sock+0x34/0xa0
      [  614.560318]  tcp_sendmsg+0x40/0x58
      [  614.571053]  inet_sendmsg+0x40/0x68
      [  614.582061]  sock_sendmsg+0x18/0x30
      [  614.593074]  xs_sendpages+0x218/0x328
      [  614.604506]  xs_tcp_send_request+0xa0/0x1b8
      [  614.617461]  xprt_transmit+0xc8/0x4f0
      [  614.628943]  call_transmit+0x8c/0xa0
      [  614.640028]  __rpc_execute+0xbc/0x6f8
      [  614.651380]  rpc_async_schedule+0x28/0x48
      [  614.663846]  process_one_work+0x298/0x6a8
      [  614.676299]  worker_thread+0x40/0x490
      [  614.687687]  kthread+0x134/0x138
      [  614.697804]  ret_from_fork+0x10/0x18
      [  614.717319] xilinx_axienet 7fe00000.ethernet eth0: Link is Down
      [  615.748343] xilinx_axienet 7fe00000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
      
      Since tasklets are not really popular anymore anyway, lets convert this
      over to a work queue, which can sleep and thus can take the MDIO mutex.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      24201a64
    • Andre Przywara's avatar
      net: xilinx: temac: Relax Kconfig dependencies · e8b6c54f
      Andre Przywara authored
      Similar to axienet, the temac driver is now architecture agnostic, and
      can be at least compiled for several architectures.
      Especially the fact that this is a soft IP for implementing in FPGAs
      makes the current restriction rather pointless, as it could literally
      appear on any architecture, as long as an FPGA is connected to the bus.
      
      The driver hasn't been actually tried on any hardware, it is just a
      drive-by patch when doing the same for axienet (a similar patch for
      axienet is already merged).
      
      This (temac and axienet) have been compile-tested for:
      alpha hppa64 microblaze mips64 powerpc powerpc64 riscv64 s390 sparc64
      (using kernel.org cross compilers).
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e8b6c54f
    • Vladyslav Tarasiuk's avatar
      ethtool: fix incorrect tx-checksumming settings reporting · 9d648fb5
      Vladyslav Tarasiuk authored
      Currently, ethtool feature mask for checksum command is ORed with
      NETIF_F_FCOE_CRC_BIT, which is bit's position number, instead of the
      actual feature bit - NETIF_F_FCOE_CRC.
      
      The invalid bitmask here might affect unrelated features when toggling
      TX checksumming. For example, TX checksumming is always mistakenly
      reported as enabled on the netdevs tested (mlx5, virtio_net).
      
      Fixes: f70bb065 ("ethtool: update mapping of features to legacy ioctl requests")
      Signed-off-by: default avatarVladyslav Tarasiuk <vladyslavt@mellanox.com>
      Reviewed-by: default avatarMichal Kubecek <mkubecek@suse.cz>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9d648fb5
    • Dejin Zheng's avatar
      net: phy: mdio-mux-bcm-iproc: use readl_poll_timeout() to simplify code · c9c1fd62
      Dejin Zheng authored
      use readl_poll_timeout() to replace the poll codes for simplify
      iproc_mdio_wait_for_idle() function
      Signed-off-by: default avatarDejin Zheng <zhengdejin5@gmail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c9c1fd62
    • David S. Miller's avatar
      Merge tag 'wireless-drivers-next-2020-03-24' of... · 5ef8c665
      David S. Miller authored
      Merge tag 'wireless-drivers-next-2020-03-24' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next
      
      Kalle Valo says:
      
      ====================
      wireless-drivers-next patches for v5.7
      
      Second set of patches for v5.7. Lots of cleanup patches this time, but
      of course various new features as well fixes.
      
      When merging with wireless-drivers this pull request has a conflict in:
      
      drivers/net/wireless/intel/iwlwifi/pcie/drv.c
      
      To solve that just drop the changes from commit cf52c8a7 in
      wireless-drivers and take the hunk from wireless-drivers-next as is.
      The list of specific subsystem device IDs are not necessary after
      commit d6f2134a (in wireless-drivers-next) anymore, the detection
      is based on other characteristics of the devices.
      
      Major changes:
      
      qtnfmac
      
      * support WPA3 SAE and OWE in AP mode
      
      ath10k
      
      * support for getting btcoex settings from Device Tree
      
      * support QCA9377 SDIO device
      
      ath11k
      
      * add HE rate accounting
      
      * add thermal sensor and cooling devices
      
      mt76
      
      * MT7663 support for the MT7615 driver
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5ef8c665
    • David S. Miller's avatar
      Merge branch 'PTP_CLK-pin-configuration-for-SJA1105-DSA-driver' · 9970de8b
      David S. Miller authored
      Vladimir Oltean says:
      
      ====================
      PTP_CLK pin configuration for SJA1105 DSA driver
      
      This series adds support for the PTP_CLK pin on SJA1105 to be configured
      via the PTP subsystem, in the "periodic output" and "external timestamp
      input" modes.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9970de8b
    • Vladimir Oltean's avatar
      net: dsa: sja1105: configure the PTP_CLK pin as EXT_TS or PER_OUT · 747e5eb3
      Vladimir Oltean authored
      The SJA1105 switch family has a PTP_CLK pin which emits a signal with
      fixed 50% duty cycle, but variable frequency and programmable start time.
      
      On the second generation (P/Q/R/S) switches, this pin supports even more
      functionality. The use case described by the hardware documents talks
      about synchronization via oneshot pulses: given 2 sja1105 switches,
      arbitrarily designated as a master and a slave, the master emits a
      single pulse on PTP_CLK, while the slave is configured to timestamp this
      pulse received on its PTP_CLK pin (which must obviously be configured as
      input). The difference between the timestamps then exactly becomes the
      slave offset to the master.
      
      The only trouble with the above is that the hardware is very much tied
      into this use case only, and not very generic beyond that:
       - When emitting a oneshot pulse, instead of being told when to emit it,
         the switch just does it "now" and tells you later what time it was,
         via the PTPSYNCTS register. [ Incidentally, this is the same register
         that the slave uses to collect the ext_ts timestamp from, too. ]
       - On the sync slave, there is no interrupt mechanism on reception of a
         new extts, and no FIFO to buffer them, because in the foreseen use
         case, software is in control of both the master and the slave pins,
         so it "knows" when there's something to collect.
      
      These 2 problems mean that:
       - We don't support (at least yet) the quirky oneshot mode exposed by
         the hardware, just normal periodic output.
       - We abuse the hardware a little bit when we expose generic extts.
         Because there's no interrupt mechanism, we need to poll at double the
         frequency we expect to receive a pulse. Currently that means a
         non-configurable "twice a second".
      Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
      Acked-by: default avatarRichard Cochran <richardcochran@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      747e5eb3