- 13 Jun, 2023 30 commits
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Konrad Dybcio authored
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 5f82b9cd ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-7-b4a985f57b8b@linaro.org
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Konrad Dybcio authored
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: c83545d9 ("arm64: dts: sdm845: Add rpmh-rsc node") Signed-off-by:
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Konrad Dybcio authored
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 07c8ded6 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Signed-off-by:
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Konrad Dybcio authored
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
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Konrad Dybcio authored
The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 6bd20c54 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by:
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Konrad Dybcio authored
Add the PSCI idle states so that the CPU (among other things) can reach lower power states. Signed-off-by:
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Anusha Rao authored
In IPQ SoCs, bootloader will collect the system RAM contents upon crash for post-morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loss of some data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable Signed-off-by:
Anusha Rao <quic_anusha@quicinc.com> Reviewed-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Kathiravan T authored
Add the initial device tree support for the Reference Design Platform(RDP) 474 based on IPQ5332 family of SoC. This patch carries the support for Console UART, eMMC, I2C and GPIO based buttons. Signed-off-by:
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Kathiravan T authored
Document the MI01.9 (Reference Design Platform 474) board based on IPQ5332 family of SoCs. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Srinivas Kandagatla authored
Soundwire controllers on sc8280xp needs an explicit reset, add support for this. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Bjorn Andersson authored
Merge the SC8280XP LPASSCC DeviceTree bindings in order to get access to the newly added reset defines.
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Srinivas Kandagatla authored
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by:
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Srinivas Kandagatla authored
The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by:
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Krzysztof Kozlowski authored
Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by:
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Krzysztof Kozlowski authored
Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by:
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Krzysztof Kozlowski authored
Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by:
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Krzysztof Kozlowski authored
Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by:
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Rohit Agarwal authored
Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by:
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Rohit Agarwal authored
Document the SDX75 platform binding and also the boards using it. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Bjorn Andersson authored
Merge the SDX75 GCC DeviceTree binding, in order to get access to the clock defines in the DeviceTree source.
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Neil Armstrong authored
The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
There's no reason to keep the RTC disabled, it has been tested and is functional on the SM8550 QRD and MTP boards. Reviewed-by:
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Neil Armstrong authored
The QRD features a notification LED connected to the pm8550. Configure the RGB led controlled by the PMIC PWM controller. Reviewed-by:
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Neil Armstrong authored
Add the PWM function to the pm8550 dtsi, this is usually used to drive RGB leds on platforms using this PMIC. Reviewed-by:
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Bjorn Andersson authored
The DisplayPort blocks are powered by MMCX and should be described as such to ensure that power votes are done on the right resource. This also solves the problem that sync_state is unaware of the DP controllers needing MMCX to be kept alive during boot. As such this change also fixes occasionally seen crashes during boot due to undervoltage of MMCX. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bjorn Andersson authored
The adreno smmu should be compatible with qcom,adreno-smmu as well for per-process page tables to work. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
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Bjorn Andersson authored
&dispcc status was changed to okay by default in the platform, no need to do it again in the board. Fixes: 2ce38cc1 ("arm64: dts: qcom: sc8180x: Introduce Primus") Signed-off-by:
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Neil Armstrong authored
Add the Display Port controller subnode to the MDSS node. Reviewed-by:
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Neil Armstrong authored
"low" was written "lov", fix this. Fixes: 99d33ee6 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels") Reviewed-by:
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Andrew Halaney authored
With wider usage on more boards, there have been reports of the following: [ 315.016174] qcom-ethqos 20000.ethernet eth0: no phy at addr -1 [ 315.016179] qcom-ethqos 20000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) which has been fairly random and isolated to specific boards. Early reports were written off as a hardware issue, but it has been prevalent enough on boards that theory seems unlikely. In bring up of a newer piece of hardware, similar was seen, but this time _consistently_. Moving the reset to the mdio bus level (which isn't exactly a lie, it is the only device on the bus so one could model it as such) fixed things on that platform. Analysis on sa8540p-ride shows that the phy's reset is not being handled during the OUI scan if the reset lives in the phy node: # gpio 752 is the reset, and is active low, first mdio reads are the OUI modprobe-420 [006] ..... 154.738544: mdio_access: stmmac-0 read phy:0x08 reg:0x02 val:0x0141 modprobe-420 [007] ..... 154.738665: mdio_access: stmmac-0 read phy:0x08 reg:0x03 val:0x0dd4 modprobe-420 [004] ..... 154.741357: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.741358: gpio_direction: 752 out (0) modprobe-420 [004] ..... 154.741360: gpio_value: 752 set 0 modprobe-420 [006] ..... 154.762751: gpio_value: 752 set 1 modprobe-420 [007] ..... 154.846857: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.937824: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-420 [004] ..... 154.937932: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 Moving it to the bus level, or specifying the OUI in the phy's compatible ensures the reset is handled before any mdio access Here is tracing with the OUI approach (which skips scanning the OUI): modprobe-549 [007] ..... 63.860295: gpio_value: 752 set 1 modprobe-549 [007] ..... 63.860297: gpio_direction: 752 out (0) modprobe-549 [007] ..... 63.860299: gpio_value: 752 set 0 modprobe-549 [004] ..... 63.882599: gpio_value: 752 set 1 modprobe-549 [005] ..... 63.962132: gpio_value: 752 set 1 modprobe-549 [006] ..... 64.049379: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-549 [006] ..... 64.049490: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 The OUI approach is taken given the description matches the situation perfectly (taken from ethernet-phy.yaml): - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: If the PHY reports an incorrect ID (or none at all) then the compatible list may contain an entry with the correct PHY ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, this is the chip vendor OUI bits 19:24, followed by 10 bits of a vendor specific ID. With this in place the sa8540p-ride's phy is probing consistently, so it seems the floating reset during mdio access was the issue. In either case, it shouldn't be floating so this improves the situation. The below link discusses some of the relationship of mdio, its phys, and points to this OUI compatible as a way to opt out of the OUI scan pre-reset handling which influenced this decision. Link: https://lore.kernel.org/all/dca54c57-a3bd-1147-63b2-4631194963f0@gmail.com/ Fixes: 57827e87 ("arm64: dts: qcom: sa8540p-ride: Add ethernet nodes") Signed-off-by:Andrew Halaney <ahalaney@redhat.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
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- 30 May, 2023 10 commits
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Bjorn Andersson authored
Introduce support for the Lenovo Flex 5G laptop, built on the Qualcomm SC8180X platform. Supported peripherals includes keyboard, touchpad, UFS storage, external USB and WiFi. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Bjorn Andersson authored
Introduce support for the SC8180X reference device, aka Primus, with debug UART, regulators, UFS and USB support. Signed-off-by:
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Vinod Koul authored
SC8180X based platforms have PM8150, PM8150C, PMC8180 and SMB2351 PMICs, so add these as well Co-developed-by:
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Vinod Koul authored
This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with dsi0/1, dp0/1 and edp subnodes as found in this SoC Co-developed-by:
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Vinod Koul authored
This patch adds remoteprocs, wifi and usb and usb phy nodes for this SoC Co-developed-by:
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Vinod Koul authored
This patch adds PCIe instances found on this SoC Co-developed-by:
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Vinod Koul authored
This patch adds qup instances and i2c, spi, serial ports Co-developed-by:
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Vinod Koul authored
This patch adds tsens nodes and thermal zones for sc8180x SoC Co-developed-by:
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Vinod Koul authored
This add interconnect nodes and add LMH to sc8180x SoC dtsi Co-developed-by:
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Bjorn Andersson authored
Introduce a base dtsi for the Qualcomm SC8180x platform, with CPUs, global clock controller, SMMU, rpmh clocks, rpmh power-domains, CPUfreq etc Signed-off-by:
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