- 20 May, 2022 2 commits
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Miquel Raynal authored
NAND core: * Print offset instead of page number for bad blocks Raw NAND controller drivers: * Cadence: Fix possible null-ptr-deref in cadence_nand_dt_probe() * CS553X: simplify the return expression of cs553x_write_ctrl_byte() * Davinci: Remove redundant unsigned comparison to zero * Denali: Use managed device resources * GPMI: - Add large oob bch setting support - Rename the variable ecc_chunk_size - Uninline the gpmi_check_ecc function - Add strict ecc strength check - Refactor BCH geometry settings function * Intel: Fix possible null-ptr-deref in ebu_nand_probe() * MPC5121: Check before clk_disable_unprepare() not needed * Mtk: - MTD_NAND_ECC_MEDIATEK should depend on ARCH_MEDIATEK - Also parse the default nand-ecc-engine property if available - Make mtk_ecc.c a separated module * OMAP ELM: - Convert the bindings to yaml - Describe the bindings for AM64 ELM - Add support for its compatible * Renesas: Use runtime PM instead of the raw clock API and update the bindings accordingly * Rockchip: Check before clk_disable_unprepare() not needed * TMIO: Check return value after calling platform_get_resource() Raw NAND chip driver: * Kioxia: Add support for TH58NVG3S0HBAI4 and TC58NVG0S3HTA00 SPI-NAND chip drivers: * Gigadevice: - Add support for: - GD5FxGM7xExxG - GD5F{2,4}GQ5xExxG - GD5F1GQ5RExxG - GD5FxGQ4xExxG - Fix Quad IO for GD5F1GQ5UExxG * XTX: Add support for XT26G0xA Signed-off-by:Miquel Raynal <miquel.raynal@bootlin.com>
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Miquel Raynal authored
SPI NOR core changes: - Read back written SR value to make sure the write was done correctly. - Introduce a common function for Read ID that manufacturer drivers can use to verify the Octal DTR switch worked correctly. - Add helpers for read/write any register commands so manufacturer drivers don't open code it every time. - Clarify rdsr dummy cycles documentation. - Add debugfs entry to expose internal flash parameters and state. SPI NOR manufacturer drivers changes: - Add support for Winbond W25Q512NW-IM, and Eon EN25QH256A. - Move spi_nor_write_ear() to Winbond module since only Winbond flashes use it. - Rework Micron and Cypress Octal DTR enable methods to improve readability. - Use the common Read ID function to verify switch to Octal DTR mode for Micron and Cypress flashes. - Skip polling status on volatile register writes for Micron and Cypress flashes since the operation is instant. Signed-off-by:
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- 17 May, 2022 1 commit
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Yang Yingliang authored
Clock source is prepared and enabled by clk_prepare_enable() in probe function, but not disabled or unprepared in remove function. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
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- 16 May, 2022 8 commits
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Mikhail Zhilkin authored
Extend fixed-partitions binding for support of Sercomm partition parser (add "sercomm,sc-partitions" compatible). Signed-off-by:
Mikhail Zhilkin <csharper2005@gmail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Mikhail Zhilkin authored
Add "sercomm" vendor prefix for "Sercomm (Suzhou) Corporation". Company website: Link: https://www.sercomm.com/Signed-off-by:
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Vincent Whitchurch authored
Currently phram always uses ioremap(), but this is unnecessary when normal memory is used. If the reserved-memory node does not specify the no-map property, indicating it should be mapped as system RAM and ioremap() cannot be used on it, use a cached mapping using memremap(MEMREMAP_WB) instead. On one of my systems this improves read performance by ~70%. (Note that this driver has always used normal memcpy/memset functions on memory obtained from ioremap(), which sparse doesn't like. There is no memremap() variant which maps exactly to ioremap() on all architectures, so that behaviour of the driver is not changed to avoid affecting existing users, but the sparse warnings are suppressed in the moved code with __force.) Signed-off-by:
Vincent Whitchurch <vincent.whitchurch@axis.com> Signed-off-by:
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Rafał Miłecki authored
Until this change MTD subsystem supported handling partitions only with MTD partitions parsers. That's a specific / limited API designed around partitions. Some MTD partitions may however require different handling. They may contain specific data that needs to be parsed and somehow extracted. For that purpose MTD subsystem should allow binding of standard platform drivers. An example can be U-Boot (sub)partition with environment variables. There exist a "u-boot,env" DT binding for MTD (sub)partition that requires an NVMEM driver. Ref: 5db1c2db ("dt-bindings: nvmem: add U-Boot environment variables binding") Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Signed-off-by:
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Miquel Raynal authored
This NAND controller is part of a well defined power domain handled by the runtime PM core. Let's keep the harmony with the other RZ/N1 drivers and exclusively use the runtime PM API to enable/disable the clocks. We still need to retrieve the external clock rate in order to derive the NAND timings, but that is not a big deal, we can still do that in the probe and just save this value to reuse it later. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/linux-mtd/20220513104957.257721-3-miquel.raynal@bootlin.com
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Miquel Raynal authored
Add the missing power-domain property which is needed on all the RZ/N1 SoC IPs. Suggested-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-mtd/20220513104957.257721-2-miquel.raynal@bootlin.com
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Phil Edworthy authored
All code in clk_disable_unprepare() already checks the clk ptr using IS_ERR_OR_NULL so there is no need to check it again before calling it. A lot of other drivers already rely on this behaviour, so it's safe to do so here. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
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Phil Edworthy authored
All code in clk_disable_unprepare() already checks the clk ptr using IS_ERR_OR_NULL so there is no need to check it again before calling it. A lot of other drivers already rely on this behaviour, so it's safe to do so here. Signed-off-by:
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- 12 May, 2022 4 commits
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Geert Uytterhoeven authored
The MediaTek Hardware ECC Engine is only present on MediaTek MT27xx and MT76xx SoCs. The driver for this engine is a dependency for the MediaTek NAND controller (MTD_NAND_MTK) and the MediaTek SPI NAND Flash Interface (SPI_MTK_SNFI) drivers, both of which already depend on ARCH_MEDIATEK. Hence add a dependency on ARCH_MEDIATEK to the Hardware ECC Engine driver, too, to prevent asking the user about this driver when configuring a kernel without MediaTek SoC support. Fixes: 4fd62f15 ("mtd: nand: make mtk_ecc.c a separated module") Signed-off-by:
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Minghao Chi authored
Simplify the return expression. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by:
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Rickard x Andersson authored
Add timings for Kioxia/Toshiba TH58NVG3S0HBAI4. Timings for this memory matches the timings selected for TH58NVG2S3HBAI4. This patch increases eraseblock write speed from 5248 KiB/s to 6864 KiB/s and erase block read speed from 8542 KiB/s to 18360 KiB/s Tested on i.MX6SX. Signed-off-by:
Rickard x Andersson <rickaran@axis.com> Signed-off-by:
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Michael Walle authored
The intention was to print the JEDEC ID in the following format: nn nn nn In this case format specifier has to be "%*ph". Fix it. Fixes: 0257be79 ("mtd: spi-nor: expose internal parameters via debugfs") Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Michael Walle <michael@walle.cc> Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220512112027.3771734-1-michael@walle.cc
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- 09 May, 2022 4 commits
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Leon M. George authored
This patch allows accessing the upper 16m on the A variant (EN25QH256A) of the EN25QH256 that shares same JEDEC ID. Without this patch, addr_with is detected to be '4' but the read_opcode is a plain READ (supporting only 3 byte addresses). Setting PARSE_SFDP is enough to detect the read_opcode READ_4B on the A variant. READ_4B is not available on the no-A variant. Both variants support 4-byte address mode (spi_nor_set_4byte_addr_mode) but that is prone to breaking on unexpected reboots if the reset pin isn't connected (broken-flash-reset). The no-A variant supports a 'high bank latch mode' that affects read, program, and erase commands - similar to the extended address register (EAR). The HBL bit is manipulated using the ENHBL (0x67) and EXHBL (0x98) opcodes. Should it become necessary to distinguish the two variants in the future, the A variant sets the SNOR_HWCAPS_READ_1_1_4 SFDP param - the no-A variant doesn't. Tested with and without fast read on the A variant only. Signed-off-by:
Leon M. George <leon@georgemail.eu> Signed-off-by:
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Shaik Sajida Bhanu authored
Add support for winbond W25Q512NW-IM chip. Below are the tests done: 1. Verified flashing binary image on spi card using flashrom tool. 2. Verified OTP support, below are the test results: localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/jedec_id ef8020 localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/manufacturer winbond localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/partname w25q512nwm localhost / # hexdump /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/sp i16/spi16.0/spi-nor/sfdp 0000000 4653 5044 0106 ff01 0600 1001 0080 ff00 0000010 0084 0201 00d0 ff00 ffff ffff ffff ffff 0000020 6800 6c65 6f6c 7720 726f 646c ffff ffff 0000030 ffff ffff ffff ffff ffff ffff ffff ffff * 0000080 20e5 fffb ffff 1fff eb44 6b08 3b08 bb42 0000090 fffe ffff ffff 0000 ffff eb40 200c 520f 00000a0 d810 0000 0233 00a6 e781 d914 63e9 3376 00000b0 757a 757a bdf7 5cd5 f719 ff5d 70e9 a5f9 00000c0 ffff ffff ffff ffff ffff ffff ffff ffff 00000d0 0aff fff0 ff21 ffdc 00000d8 localhost / # md5sum /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi 16/spi16.0/spi-nor/sfdp 106d89d6c049110bc94c01517cb4ce24 /sys/bus/platform/devices/soc@0/88dc000.spi/ spi_master/spi16/spi16.0/spi-nor/sfdp Signed-off-by:
Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by:
Doug Anderson <dianders@chromium.org> Reviewed-by:
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Michael Walle authored
There is no way to gather all information to verify support for a new flash chip. Also if you want to convert an existing flash chip to the new SFDP parsing, there is not enough information to determine if the flash will work like before. To ease this development, expose internal parameters via the debugfs. Signed-off-by:
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Michael Walle authored
The function will also be used by the debugfs module. Signed-off-by:
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- 02 May, 2022 1 commit
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Michael Walle authored
The "Extended Address Register" is winbond specific. If the flash is larger than 16MiB and is used in 3 byte address mode, it is used to set the remaining address bits. Move the write_ear() function, the opcode macros and the spimem op template into the winbond module and rename them accordingly. Signed-off-by:
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- 29 Apr, 2022 1 commit
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Michael Walle authored
The rdsr dummy cycles are only used by the 8d-8d-8d mode. Mention that in the documentation. Signed-off-by:
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- 28 Apr, 2022 4 commits
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Tokunori Ikegami authored
Signed-off-by:
Tokunori Ikegami <ikegami.t@gmail.com> Acked-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
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Tokunori Ikegami authored
It is for the model number 01, 02, V1 and V2. Signed-off-by:
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Tokunori Ikegami authored
Since commit dfeae107("mtd: cfi_cmdset_0002: Change write buffer to check correct value") buffered writes fail on S29GL064N. This is because, on S29GL064N, reads return 0xFF at the end of DQ polling for write completion, where as, chip_good() check expects actual data written to the last location to be returned post DQ polling completion. Fix is to revert to using chip_good() for S29GL064N which only checks for DQ lines to settle down to determine write completion. Link: https://lore.kernel.org/r/b687c259-6413-26c9-d4c9-b3afa69ea124@pengutronix.de/ Fixes: dfeae107("mtd: cfi_cmdset_0002: Change write buffer to check correct value") Cc: stable@vger.kernel.org Signed-off-by:
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Tokunori Ikegami authored
This is a preparation patch for the S29GL064N buffer writes fix. There is no functional change. Link: https://lore.kernel.org/r/b687c259-6413-26c9-d4c9-b3afa69ea124@pengutronix.de/ Fixes: dfeae107("mtd: cfi_cmdset_0002: Change write buffer to check correct value") Signed-off-by:
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- 27 Apr, 2022 15 commits
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Miquel Raynal authored
Mediatek ECC changes: * Also parse the default nand-ecc-engine property if available * Make mtk_ecc.c a separated module Signed-off-by: -
Chuanhong Guo authored
The recently added ECC engine support introduced a generic property named nand-ecc-engine for ecc engine phandle. This patch adds support for this new property. Signed-off-by:
Chuanhong Guo <gch981213@gmail.com> Signed-off-by:
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Chuanhong Guo authored
this code will be used in mediatek snfi spi-mem controller with pipelined ECC engine. Signed-off-by:
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Yang Yingliang authored
It will cause null-ptr-deref if platform_get_resource() returns NULL, we need check the return value. Signed-off-by:
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Yang Yingliang authored
It will cause null-ptr-deref when using 'res', if platform_get_resource() returns NULL, so move using 'res' after devm_ioremap_resource() that will check it to avoid null-ptr-deref. Fixes: 0b1039f0 ("mtd: rawnand: Add NAND controller support on Intel LGM SoC") Signed-off-by:
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Yang Yingliang authored
It will cause null-ptr-deref when using 'res', if platform_get_resource() returns NULL, so move using 'res' after devm_ioremap_resource() that will check it to avoid null-ptr-deref. And use devm_platform_get_and_ioremap_resource() to simplify code. Fixes: ec4ba01e ("mtd: rawnand: Add new Cadence NAND driver to MTD subsystem") Signed-off-by:
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Tudor Ambarus authored
Writing volatile registers are instant according to Micron and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by:
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Tudor Ambarus authored
Writing volatile registers are instant according to Cypress and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by:
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Tudor Ambarus authored
Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by:
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Tudor Ambarus authored
Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Add debug messages in case spi_nor_read_id() fails. Signed-off-by:
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Tudor Ambarus authored
Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Add dev_dbg messages in case spi_nor_read_id() fails. Signed-off-by:
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Tudor Ambarus authored
There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by:
Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by:
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Tudor Ambarus authored
Use spi_nor_read_id() core method to avoid duplication of code. Now the ID is read on the full SPI_NOR_MAX_ID_LEN instead of round_up(nor->info->id_len, 2), but it doesn't harm to read more ID bytes, so the change comes with no secondary effects. dev_dbg messages in case spi_nor_read_id() fails, will be added in a further patch after we split the octal DTR enable/disable methods. Signed-off-by:
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Tudor Ambarus authored
RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by:
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Tudor Ambarus authored
In case spi_nor_match_name() returned NULL, the auto detection was issued twice. There's no reason to try to detect the same chip twice, do the auto detection only once. Signed-off-by:
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