- 27 Sep, 2020 1 commit
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Fabien Parent authored
Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200907110221.1691168-1-fparent@baylibre.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 21 Sep, 2020 2 commits
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.10-1 * Add last part of cleanup Cherryview driver to align with other drivers * Due to above clean up Cherryview and Baytrail drivers to use common API The following is an automated git shortlog grouped by driver: baytrail: - Switch to use intel_pinctrl_get_soc_data() cherryview: - Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs - Switch to use intel_pinctrl_get_soc_data() - Utilize temporary variable to hold device pointer - Switch to use struct intel_pinctrl - Move custom community members to separate data struct - Drop stale comment intel: - Update header block to reflect direct dependencies - Extract intel_pinctrl_get_soc_data() helper for wider use
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.10 - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1, - Three more conversion of DT bindings to json-schema, - Group all Renesas pinctrl drivers and improve visual Kconfig structure, - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, - Minor fixes and improvements.
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- 15 Sep, 2020 12 commits
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Geert Uytterhoeven authored
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
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Geert Uytterhoeven authored
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by:
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Geert Uytterhoeven authored
The RZ/N1 pin control driver does not use pin groups or pin functions, so there is no need to select GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. Signed-off-by:
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Geert Uytterhoeven authored
Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
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Geert Uytterhoeven authored
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by:
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Geert Uytterhoeven authored
For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 42556242 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Acked-by:
Jacopo Mondi <jacopo@jmondi.org> Acked-by:
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Kuninori Morimoto authored
Sort each driver by description title in alphabetical order. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87h7ssy4qy.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
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Kuninori Morimoto authored
Now, Renesas Pin Control drivers are under menu, but current descriptions are not aligned. This patch aligns them. - RZ/A2 gpio and pinctrl driver - RZ/N1 pinctrl driver - Emma Mobile EV2 pin control support - R-Mobile APE6 pin control support - R-Mobile A1 pin control support - RZ/G1H pin control support - RZ/G1M pin control support + pin control support for RZ/A2 + pin control support for RZ/N1 + pin control support for Emma Mobile EV2 + pin control support for R-Mobile APE6 + pin control support for R-Mobile A1 + pin control support for RZ/G1H + pin control support for RZ/G1M Signed-off-by: -
Kuninori Morimoto authored
Renesas related pinctrl CONFIGs are located in many places, which is confusing. This patch collects them into the same place, grouped in a new "Renesas pinctrl drivers" menu. This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder. Signed-off-by: -
Kuninori Morimoto authored
It is "Emma Mobile EV2" not "AV2". This patch tidies it up. Reported-by:
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Geert Uytterhoeven authored
Convert the Renesas Pin Function Controller (PFC) Device Tree binding documentation to json-schema. Document missing properties. Drop deprecated and obsolete #gpio-range-cells property. Update the example to match reality. Drop consumer examples, as they do not belong here. Signed-off-by:
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- 12 Sep, 2020 13 commits
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Thierry Reding authored
driver_deferred_probe_check_state() may return -ETIMEDOUT instead of -EPROBE_DEFER after all built-in drivers have been probed. This can cause issues for built-in drivers that depend on resources provided by loadable modules. One such case happens on Tegra where I2C controllers are used during early boot to set up the system PMIC, so the I2C driver needs to be a built-in driver. At the same time, some instances of the I2C controller depend on the DPAUX hardware for pinmuxing. Since the DPAUX is handled by the display driver, which is usually not built-in, the pin control states will not become available until after the root filesystem has been mounted and the display driver loaded from it. Fixes: bec6c0ec ("pinctrl: Remove use of driver_deferred_probe_check_state_continue()") Suggested-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200825143348.1358679-1-thierry.reding@gmail.comSigned-off-by:
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Martin DEVERA authored
I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant DTS part: compatible = "semtech,sx1502q"; gpio4_cfg_pins: gpio2-cfg { pins = "gpio5"; output-high; }; And part of OOPS: [ 0.673996] [<c023cfa6>] (gpiochip_get_data) from [<c023b235>] (sx150x_gpio_direction_output+0xd) [ 0.683259] [<c023b235>] (sx150x_gpio_direction_output) from [<c023b363>] (sx150x_pinconf_set+0x) [ 0.692796] [<c023b363>] (sx150x_pinconf_set) from [<c0238fef>] (pinconf_apply_setting+0x39/0x7e) [ 0.701635] [<c0238fef>] (pinconf_apply_setting) from [<c0236c77>] (pinctrl_commit_state+0xa5/0x) [ 0.710648] [<c0236c77>] (pinctrl_commit_state) from [<c0237e03>] (pinctrl_enable+0xff/0x1d4) [ 0.719139] [<c0237e03>] (pinctrl_enable) from [<c023b791>] (sx150x_probe+0x1a3/0x358) [ 0.727027] [<c023b791>] (sx150x_probe) from [<c02c38bf>] (i2c_device_probe+0x1bb/0x1dc) The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output but gpio is not setup yet. Patch below fixes it but I'm not sure whether is it correct. Link: https://lore.kernel.org/r/f32130bf-cfd4-b1bf-538c-dbc9ee2d947a@eaxlabs.czSigned-off-by:Martin DEVERA <devik@eaxlabs.cz> Signed-off-by:
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Heiko Stuebner authored
The Rockchip pinctrl driver needs to handle information from Devicetree so only makes sense getting compiled on systems with CONFIG_OF enabled. This also fixes a problem found by the "kernel-test-robot" when compiling the driver on test-builds that do not have CONFIG_OF enabled: drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups': >> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration] 2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | pinconf_generic_dump_config drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register': >> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node' 3473 | gc->of_node = bank->of_node; Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.deSigned-off-by:
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Yangtao Li authored
This commit introduces support for the pin controller on A100. Signed-off-by:
Yangtao Li <frank@allwinnertech.com> Acked-by:
Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.comSigned-off-by:
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Yangtao Li authored
Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines. Signed-off-by:
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Yangtao Li authored
Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else. Signed-off-by:
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Nobuhiro Iwamatsu authored
Add pinctrl support to Toshiba Visconti SoCs. Signed-off-by:
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by:
Punit Agrawal <punit1.agrawal@toshiba.co.jp> Link: https://lore.kernel.org/r/20200909204336.2558-3-nobuhiro1.iwamatsu@toshiba.co.jpSigned-off-by:
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Nobuhiro Iwamatsu authored
Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. Signed-off-by:
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Rikard Falkeborn authored
The only usage of s900_padinfo[] is to assign it to the padinfo field in the owl_pinctrl_soc_data struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200830224311.36994-4-rikard.falkeborn@gmail.comSigned-off-by:
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Rikard Falkeborn authored
The only usage of s700_padinfo[] is to assign it to the padinfo field in the owl_pinctrl_soc_data struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by:
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Rikard Falkeborn authored
The only usage of owl_pinctrl_ops and owl_pinmux_ops is to assign their addresses to the pctlops and the pmxops fields in the pinctrl_desc struct, which are const pointers. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
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Thomas Preston authored
On page 23 of the datasheet [0] it says "The register remains unchanged until the interrupt is cleared via a read of INTCAP or GPIO." Include INTCAPA and INTCAPB registers in precious range, so that they aren't accidentally cleared when we read via debugfs. [0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf Fixes: 8f38910b ("pinctrl: mcp23s08: switch to regmap caching") Signed-off-by:
Thomas Preston <thomas.preston@codethink.co.uk> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200828213226.1734264-3-thomas.preston@codethink.co.ukSigned-off-by:
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Thomas Preston authored
The mcp23x17_regmap is initialised with structs named "mcp23x16". However, the mcp23s08 driver doesn't support the MCP23016 device yet, so this appears to be a typo. Fixes: 8f38910b ("pinctrl: mcp23s08: switch to regmap caching") Signed-off-by:
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- 07 Sep, 2020 1 commit
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Hans de Goede authored
One some devices the GPIO should output the inverted value from what device-drivers / ACPI code expects. The reason for this is unknown, perhaps these systems use an external buffer chip on the GPIO which inverts the signal. The BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag. Before this commit we would unconditionally clear all INVRXTX flags, including the CHV_PADCTRL1_INVRXTX_TXDATA flag when a GPIO is requested by a driver (from chv_gpio_request_enable()). This breaks systems using this setup. Specifically it is causing problems for systems with a goodix touchscreen, where the BIOS sets the INVRXTX_TXDATA flag on the GPIO used for the touchscreen's reset pin. The goodix touchscreen driver by defaults configures this pin as input (relying on the pull-up to keep it high), but the clearing of the INVRXTX_TXDATA flag done by chv_gpio_request_enable() causes it to be driven low for a brief time before the GPIO gets set to input mode. This causes the touchscreen controller to get reset. On most CHT devs with this touchscreen this leads to: [ 31.596534] Goodix-TS i2c-GDIX1001:00: i2c test failed attempt 1: -121 The driver retries this though and then everything is fine. But during reset the touchscreen uses its interrupt pin as bootstrap to determine which i2c address to use and on the Acer One S1003 the spurious reset caused by the clearing of the INVRXTX_TXDATA flag causes the controller to come back up again on the wrong i2c address, breaking things. This commit fixes both the -121 errors, as well as the total breakage on the Acer One S1003, by making chv_gpio_clear_triggering() not clear the INVRXTX_TXDATA flag if the pin is already configured as a GPIO. Note that chv_pinmux_set_mux() does still unconditionally clear the flag, so this only affects GPIO usage. Fixes: a7d4b171 ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices") Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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- 31 Aug, 2020 1 commit
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Lad Prabhakar authored
Add pins, groups and functions for the CAN{0,1} interface. Signed-off-by:Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200825095448.13093-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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- 28 Aug, 2020 1 commit
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Andy Shevchenko authored
Print particular message in each of error case in the ->probe(). While here, use dev_err_probe() for that. Signed-off-by:
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- 27 Aug, 2020 9 commits
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Zhiyong Tao authored
This commit includes pinctrl driver for mt8192. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20200817001702.1646-4-zhiyong.tao@mediatek.comSigned-off-by:
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Zhiyong Tao authored
The commit adds mt8192 compatible node in binding document. Signed-off-by:
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Zhiyong Tao authored
This patch adds pinctrl file for mt8192. Signed-off-by:
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Cristian Ciocaltea authored
Update the pinctrl binding entry to match all members of Actions Semi Owl SoCs. Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/1a9eb2b12c151d4d765d2aa74dc9cd58b3c117dc.1596461275.git.cristian.ciocaltea@gmail.comSigned-off-by:
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Cristian Ciocaltea authored
Add pinctrl and gpio driver for Actions Semi S500 SoC. The driver supports pinctrl, pinmux, pinconf, gpio and interrupt functions using a set of registers shared between gpio and pinctrl. Signed-off-by:
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Cristian Ciocaltea authored
Add pinctrl and gpio bindings for Actions Semi S500 SoC. Signed-off-by:
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Bartosz Dudziak authored
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration with pinctrl framework for msm8226 SoC. - Initial formatting and style was taken from the msm8x74 pinctrl driver added by Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bartosz Dudziak <bartosz.dudziak@snejp.pl> Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.plSigned-off-by:
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Bartosz Dudziak authored
Add device tree binding Documentation details for Qualcomm msm8226 pinctrl driver. - Bindings documentation was based on qcom,ipq6018-pinctrl.yaml added by Sricharan R <sricharan@codeaurora.org> and then modified for msm8226 content Signed-off-by:
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Pali Rohár authored
Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like other PCIe groups it should have been called 'pcie1_reset'. But due to backward compatibility it is not possible to change existing group name. So just add comment describing this PCIe reset functionality. Signed-off-by:
Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.orgSigned-off-by:
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