1. 28 Oct, 2004 3 commits
  2. 20 Oct, 2004 3 commits
  3. 15 Oct, 2004 3 commits
  4. 06 Oct, 2004 1 commit
  5. 14 Sep, 2004 3 commits
  6. 13 Sep, 2004 1 commit
  7. 12 Sep, 2004 3 commits
  8. 10 Sep, 2004 1 commit
  9. 08 Sep, 2004 1 commit
  10. 30 Aug, 2004 6 commits
  11. 18 Aug, 2004 5 commits
  12. 16 Aug, 2004 3 commits
  13. 14 Jul, 2004 2 commits
    • Jeff Garzik's avatar
      [netdrvr tg3] bump version and reldate · 56b32d0b
      Jeff Garzik authored
      56b32d0b
    • Anton Blanchard's avatar
      [PATCH] tg3 bug · 97975500
      Anton Blanchard authored
      
      During receive processing, the tg3 card updates rx_producer (the
      hardware position in the receive ring) and the opaque cookie. Due to PCI
      rules the stores happen in order. However the cpu may reorder the reads.
      
      In these sort of cases there is usually a data dependency between
      reading the index and looking up the data (since we use the index to
      load the data). I think all cpus except alpha guarantee the reads
      happen in order in this case.
      
      However in this particular case we load hw_idx, compare it to sw_idx and
      then use sw_idx to locate the opaque cookie. There is no data dependency
      in this case. We need a read memory barrier between the read of
      rx_producer and the opaque cookie to enforce ordering.
      
      Thanks to Olof Johansson, Michael Chan and Broadcom for their assistance
      in finding this bug.
      Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
      97975500
  14. 05 Jul, 2004 2 commits
  15. 02 Jul, 2004 2 commits
  16. 16 Jun, 2004 1 commit