- 15 Jun, 2023 40 commits
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Neha Malcom Francis authored
Document the binding for TI K3 ESM (Error Signaling Module) block. Signed-off-by:
Neha Malcom Francis <n-francis@ti.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.comSigned-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Nishanth Menon authored
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.comSigned-off-by:
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Nishanth Menon authored
Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by:
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Nishanth Menon authored
Enable wakeup_i2c. While at it, describe the board detection eeprom present on the board. Signed-off-by:
Sinthu Raja <sinthu.raja@ti.com> Reviewed-by:
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Nishanth Menon authored
Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by:
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Sinthu Raja authored
Add pinmux required to bring out the i2c and gpios on 40-pin RPi expansion header on the AM68 SK board. Signed-off-by:
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Sinthu Raja authored
The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable regions, accordingly split the existing wkup_pmx region as follows to avoid the non-addressable regions and include the rest of valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: b8545f9d ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: <stable@vger.kernel.org> # 6.3 Signed-off-by:
Thejasvi Konduru <t-konduru@ti.com> Signed-off-by:
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Udit Kumar authored
Aiases are defined at board level, so dropping from soc level Signed-off-by:
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Udit Kumar authored
Define aliases at board level Signed-off-by:
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Udit Kumar authored
Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by:
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Udit Kumar authored
main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by:
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Udit Kumar authored
There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Tony Lindgren <tony@atomide.com> Reviewed-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Udit Kumar authored
There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by:
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Nishanth Menon authored
Drop the SoC level aliases as these need to be done at board level. Signed-off-by:
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Nishanth Menon authored
Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by:
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Nishanth Menon authored
Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by:
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Nishanth Menon authored
Define the wakeup uart pin-mux for completeness. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by:
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Nishanth Menon authored
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by:
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Nishanth Menon authored
Explicitly define the pinmux rather than depend on bootloader configured pinmux for the platform. Signed-off-by:
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Nishanth Menon authored
Add product links to get reference to schematics and design files Signed-off-by:
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Nishanth Menon authored
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by:
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Nishanth Menon authored
Rather than depend on the default pinmuxes, explicitly describe the pinmux Signed-off-by:
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Andrew Davis authored
Using a phandle makes it clear which UART we are choosing without needing to resolve through an alias first. Especially useful for boards like the TI J721s2-EVM where the alias is "serial2" but it actually resolves to the 8th UART instance(main_uart8). Signed-off-by:
Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.comSigned-off-by:
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Andrew Davis authored
As the binding for "current-speed" states, this should only be used when the baud rate of an attached device cannot be detected. This is the case for our attached on-board USB-to-UART converter used for early kernel console. For all other unconnected/disabled ports this can be configured in userspace later, DT is not the place for device configuration, especially when there are already standard ways to set serial baud in userspace. Remove setting baud for all disabled serial ports and move setting it for the couple enabled ports down into the board files. Signed-off-by:
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Dasnavis Sabiya authored
Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by:
Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by:
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Nishanth Menon authored
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by:
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Nishanth Menon authored
Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by:
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Nishanth Menon authored
Enable networking for NFS and basic networking functionality. Signed-off-by:
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Nishanth Menon authored
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: 635fb18b ("arch: arm64: dts: Add support for AM69 Starter Kit") Signed-off-by:
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Nishanth Menon authored
Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by:
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Nishanth Menon authored
Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by:
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Thejasvi Konduru authored
The wkup_pmx register region in j784s4 has multiple non-addressable regions, hence the existing wkup_pmx region is split as follows to avoid the non-addressable regions. The pinctrl node offsets are also corrected as per the newly split wkup_pmx* nodes. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: 4664ebd8 ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by:
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Nishanth Menon authored
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: e20a06ac ("arm64: dts: ti: Add support for J784S4 EVM board") Signed-off-by:
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Neha Malcom Francis authored
MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's capability to re-initialise clock frequencies. CPTS and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs this reinitialisation to default frequency to be able to get 250MHz with its divider, CPTS can not get its required 200MHz with its divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side for the same reason) Signed-off-by:
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Dasnavis Sabiya authored
Add support for eMMC card connected to main sdhci0 instance. Signed-off-by:
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Nishanth Menon authored
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by:
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Nishanth Menon authored
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by:
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Nishanth Menon authored
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Nishanth Menon authored
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by:
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Nishanth Menon authored
When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by:
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