- 01 Apr, 2021 11 commits
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Arnd Bergmann authored
Merge tag 'juno-updates-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv8 Juno updates for v5.13 Couple of changes to describe PCI dma-ranges correctly which was previously removed and to enable the PCIe and DMA SMMU. * tag 'juno-updates-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Enable more SMMUs arm64: dts: juno: Describe PCI dma-ranges Link: https://lore.kernel.org/r/20210331100410.cenuhvpqoumvsk52@bogusSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.13: - A series from Dong Aisheng to update i.MX8Q device trees for adopting SS (SubSystems) based bindings. - New board support: Kontron pitx-imx8m, Engicam i.Core MX8M Mini. - A series from Adrien Grassein to add various peripheral support for imx8mm-nitrogen-r2 board. - A series from Guido Günther to update librem5-devkit device tree. - A number of patches from Michael Walle to add Root Complex Event Collector interrupt, update MTD partitions and add rtc0 alias for ls1028a-kontron-sl28 board. - Add EQOS MAC support for phyBOARD-Pollux-i.MX8MP. - Add 2x2 SFP+ cage support for clearfog-itx boards. - Small and random update for various boards. * tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (55 commits) arm64: dts: fsl-ls1028a-kontron-sl28: add rtc0 alias arm64: dts: ls1028a: move rtc alias to individual boards arm64: dts: fsl-ls1028a-kontron-sl28: combine unused partitions arm64: dts: fsl-ls1028a-kontron-sl28: move MTD partitions arm64: dts: imx8mp-evk: Improve the Ethernet PHY description arm64: dts: imx8mq-librem5-r3: Mark buck3 as always on arm64: dts: imx8mq-librem5: Hog the correct gpio arm64: dts: lx2160a-clearfog-itx: add SFP support arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART arm64: dts: imx8mn: Reorder flexspi clock-names entry arm64: dts: imx8mm: Reorder flexspi clock-names entry arm64: dts: ls1028a: set up the real link speed for ENETC port 2 arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support arm64: dts: imx: add imx8qm mek support arm64: dts: imx: add imx8qm common dts file arm64: dts: imx8qm: add dma ss support arm64: dts: imx8: split adma ss into dma and audio ss arm64: dts: imx8qm: add conn ss support arm64: dts: imx8qm: add lsio ss support arm64: dts: imx8: switch to new lpcg clock binding ... Link: https://lore.kernel.org/r/20210331041019.31345-5-shawnguo@kernel.orgSigned-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linuxArnd Bergmann authored
i.MX device tree change for 5.13: - New board support: i.MX7D based reMarkable2. - Clean up imx6ql-pfla02 hog group by moving pins into corresponded client groups. - Add Netronix embedded controller for imx50-kobo-aura. - A series from Sebastian Reichel to improve GE Bx50v3 device trees. - Support I2C bus recovery for imx6qdl-wandboard by adding SCL/SDA GPIOs. - Remove unnecessary #address-cells/#size-cells from imx6qdl-gw boards. - Various small and random device tree update. * tag 'imx-dt-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (21 commits) ARM: dts: imx6: pbab01: Set USB OTG port to peripheral ARM: dts: imx6: pfla02: Fix USB vbus enable pinmuxing ARM: imx7d-remarkable2: Initial device tree for reMarkable2 ARM: dts: imx7d-mba7: Remove unsupported PCI properties ARM: dts: imx6qdl-gw*: Remove unnecessary #address-cells/#size-cells ARM: dts: imx6dl-plybas: Fix gpio-keys W=1 warnings ARM: dts: imx: bx50v3: Define GPIO line names ARM: dts: imx: bx50v3: i2c GPIOs are open drain ARM: dts: imx6q-ba16: improve PHY information ARM: dts: imx6q-ba16: add USB OTG VBUS enable GPIO ARM: dts: ls1021a: mark crypto engine dma coherent ARM: dts: colibri-imx6ull: Change drive strength for usdhc2 ARM: dts: imx6ql-pfla02: Move "hog" pins into corresponded pin groups ARM: dts: imx6qdl-phytec-pbab01: Select synchronous mode for AUDMUX ARM: dts: imx6qdl-ts7970: Drop redundant "fsl,mode" option ARM: dts: imx53-qsb: Describe the esdhc1 card detect pin ARM: dts: ls1021a: Harmonize DWC USB3 DT nodes name ARM: dts: imx6qdl-wandboard: add scl/sda gpios definitions for i2c bus recovery ARM: dts: imx: Mark IIM as syscon on i.MX51/i.MX53 ARM: dts: imx6sl-tolino-shine2hd: Add Netronix embedded controller ... Link: https://lore.kernel.org/r/20210331041019.31345-4-shawnguo@kernel.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'imx-bindgins-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX bindings update for 5.13: - Add vendor prefix for reMarkable. - Add compatible for reMarkable 2 e-Ink tablet, Kontron pITX-imx8m board, Engicam i.Core MX8M Mini devices. - Add compatbile 'fsl,imx8qm-mu' for i.MX mailbox bindings. - One correction on example clock-names in imx8qxp-lpcg bindings. * tag 'imx-bindgins-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: fsl: Add the reMarkable 2 e-Ink tablet dt-bindings: Add vendor prefix for reMarkable dt-bindings: mailbox: mu: add imx8qm support dt-bindings: arm: fsl: add imx8qm boards compatible string dt-bindings: arm: fsl: add Kontron pITX-imx8m board dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit dt-bindings: arm: fsl: Add Engicam i.Core MX8M Mini C.TOUCH 2.0 dt-bindings: clock: imx8qxp-lpcg: correct the example clock-names Link: https://lore.kernel.org/r/20210331041019.31345-3-shawnguo@kernel.orgSigned-off-by:
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https://github.com/Broadcom/stblinuxArnd Bergmann authored
This pull request contains Broadcom ARM64-based SoCs Device Tree changes for 5.13, please pull the following: - Rafal continues to add support for the 4908 SoCs and describes the USB PHY, firmware flash partitions and Ethernet switch and Ethernet controller. He also adds support for the TP-Link Archer C2300 V1 router and upates the Netgear R8000P and Asus GT-AC5300 routers network ports description. * tag 'arm-soc/for-5.13/devicetre-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcm4908: add Ethernet MAC addr arm64: dts: broadcom: bcm4908: add Ethernet TX irq arm64: dts: broadcom: bcm4908: set Asus GT-AC5300 port 7 PHY mode arm64: dts: broadcom: bcm4908: add TP-Link Archer C2300 V1 dt-bindings: arm: bcm: document TP-Link Archer C2300 binding arm64: dts: broadcom: bcm4908: fix switch parent node name arm64: dts: broadcom: bcm4908: describe firmware partitions arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P LEDs arm64: dts: broadcom: bcm4908: describe Netgear R8000P switch arm64: dts: broadcom: bcm4908: describe Ethernet controller arm64: dts: broadcom: bcm4908: describe USB PHY Link: https://lore.kernel.org/r/20210330184006.1451315-2-f.fainelli@gmail.comSigned-off-by:
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https://github.com/Broadcom/stblinuxArnd Bergmann authored
This pull request contains Broadcom ARM-based SoCs Device Tree changes for 5.13, please pull the following: - Rafal fixes YAML warnings for the memory nodes of BCM5301X nodes and adds support for the NVMEM NVRAM node on Linksys and Luxul WLAN routers. He also fixes up the partitions for the Linksys EA9400 to use the newly introduced parser compatible and sets the power LED to its default state. * tag 'arm-soc/for-5.13/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: BCM5301X: Set Linksys EA9500 power LED ARM: dts: BCM5301X: Fix Linksys EA9500 partitions ARM: dts: BCM5301X: Describe NVMEM NVRAM on Linksys & Luxul routers ARM: dts: BCM5301X: fix "reg" formatting in /memory node Link: https://lore.kernel.org/r/20210330184006.1451315-1-f.fainelli@gmail.comSigned-off-by:
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Arnd Bergmann authored
Merge tag 'socfpga_dts_update_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.13 - Patches from Krzysztof Kozlowski that fixes dtc warnings and dtbs_check warnings - Adjust the "cnds,read-delay" value for the Agilex devkit to 2 * tag 'socfpga_dts_update_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: intel: adjust qpsi read-delay property arm64: dts: intel: socfpga_agilex_socdk_nand: align LED node names with dtschema arm64: dts: intel: socfpga_agilex: align node names with dtschema arm64: dts: intel: socfpga_agilex: use defined for GIC interrupts arm64: dts: intel: socfpga_agilex: move usbphy out of soc node arm64: dts: intel: socfpga_agilex: remove default status=okay arm64: dts: intel: socfpga_agilex: move timer out of soc node arm64: dts: intel: socfpga_agilex: move clocks out of soc node arm64: dts: intel: socfpga: override clocks by label Link: https://lore.kernel.org/r/20210330110430.558182-2-dinguyen@kernel.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'omap-for-v5.13/dts-genpd-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for genpd support for v5.13 In order to move omap4/5 and dra7 to probe with devicetree data and genpd, we need to add the missing interconnect target module configuration for the drivers that do not still have it. This is similar to what we have already done earlier for am3 and 4 earlier. These patches are very much similar for all the three SoCs here. The dra7 changes were already available for v5.12 merge window, but were considered too late to add for v5.12. The patches for omap4 and 5 follow the same pattern, except for PCIe that is available only on dra7. We do the changes one driver at a time, and still keep the legacy property for "ti,hwmods" mostly around, except for cases when already not needed. We will be dropping the custom property and related legacy data in a follow-up series. * tag 'omap-for-v5.13/dts-genpd-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (53 commits) ARM: dts: Configure simple-pm-bus for omap5 l3 ARM: dts: Configure simple-pm-bus for omap5 l4_cfg ARM: dts: Configure simple-pm-bus for omap5 l4_per ARM: dts: Configure simple-pm-bus for omap5 l4_wkup ARM: dts: Move omap5 l3-noc to a separate node ARM: dts: Move omap5 mmio-sram out of l3 interconnect ARM: dts: Configure interconnect target module for omap5 sata ARM: dts: Configure interconnect target module for omap5 gpmc ARM: dts: Configure interconnect target module for omap5 mpu ARM: dts: Configure interconnect target module for omap5 emif ARM: dts: Configure interconnect target module for omap5 dmm ARM: dts: Prepare for simple-pm-bus for omap4 l3 ARM: dts: Configure simple-pm-bus for omap4 l4_cfg ARM: dts: Configure simple-pm-bus for omap4 l4_per ARM: dts: Configure simple-pm-bus for omap4 l4_wkup ARM: dts: Move omap4 l3-noc to a separate node ARM: dts: Move omap4 mmio-sram out of l3 interconnect ARM: dts: Configure interconnect target module for omap4 mpu ARM: dts: Configure interconnect target module for omap4 debugss ARM: dts: Configure interconnect target module for omap4 emif ... Link: https://lore.kernel.org/r/pull-1617004205-537424@atomide.com-2Signed-off-by:
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Daniel Palmer authored
All of the currently known MStar/SigmaStar ARMv7 SoCs have at least one MPLL and it seems to always be at the same place so add it to the base dtsi. Signed-off-by:
Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20210301123542.2800643-4-daniel@0x0f.com' Signed-off-by:
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Daniel Palmer authored
All of the currently known MStar/SigmaStar ARMv7 SoCs have an "xtal" clock input that is usually 24MHz and an "RTC xtal" that is usually 32KHz. The xtal input has to be connected to something so it's enabled by default. The MSC313 and MSC313E do not bring the RTC clock input out to the pins so it's impossible to connect it. The SSC8336 does bring the input out to the pins but it's not always actually connected to something. The RTC node needs to always be present because in the future the nodes for the clock muxes will refer to it even if it's not usable. The RTC node is disabled by default and should be enabled at the board level if the RTC input is wired up. Signed-off-by:
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Daniel Palmer authored
All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by:
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- 30 Mar, 2021 11 commits
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Dinh Nguyen authored
The "cnds,read-delay" value needs to be 2 for the Agilex devkit. Signed-off-by:Dinh Nguyen <dinguyen@kernel.org>
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Krzysztof Kozlowski authored
Align the LED node names with dtschema to silence dtbs_check warnings like: leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
Align the NAND, GIC and UART node names with dtschema to silence dtbs_check warnings like: arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: intc@fffc1000: $nodename:0: 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dt.yaml: serial0@ffc02000: $nodename:0: 'serial0@ffc02000' does not match '^serial(@[0-9a-f,]+)*$' Signed-off-by: -
Krzysztof Kozlowski authored
Use human-readable defines for GIC interrupt type and flag, instead of hard-coding the numbers. It makes review easier. No functional change. Signed-off-by:
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Krzysztof Kozlowski authored
The usual usb-nop-xceiv USB phy node should be under root node, to fix dtc warning: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:472.21-476.5: Warning (simple_bus_reg): /soc/usbphy@0: missing or empty reg/ranges property Signed-off-by: -
Krzysztof Kozlowski authored
New nodes are okay by default. Signed-off-by:
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Krzysztof Kozlowski authored
The ARM architected timer is part of ARM CPU design therefore by convention it should not be inside the soc node. This also fixes dtc warning like: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:410.9-416.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property Signed-off-by: -
Krzysztof Kozlowski authored
The clocks are usually not part of the SoC but provided on the board (external oscillators). Moving them out of soc node fixes dtc warning: arch/arm64/boot/dts/intel/socfpga_agilex.dtsi:111.10-137.5: Warning (simple_bus_reg): /soc/clocks: missing or empty reg/ranges property Signed-off-by: -
Krzysztof Kozlowski authored
Using full paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by:
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Stefan Riedmueller authored
Due to a hardware bug preventing the correct detection if the ID pin the USB OTG port cannot be used in otg mode. It can either be set to host or peripheral. Set it to peripheral so vbus is disabled by default. Signed-off-by:
Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Stefan Riedmueller authored
The pinmuxing for the enable pin of the usbh1 node is wrong. It needs to be muxed as GPIO. While at it, move the pinctrl to the vbus regulator since it is actually the regulator enable pin. Signed-off-by:
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- 29 Mar, 2021 18 commits
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Rafał Miłecki authored
On most BCM4908 devices MAC address can be read from the bootloader binary section containing device settings. Use NVMEM to describe that. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Rafał Miłecki authored
Set Linux default trigger to default on, just like it's normally done for power LEDs. Signed-off-by:
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Rafał Miłecki authored
Partitions are basically fixed indeed but firmware ones don't have hardcoded function ("firmware" vs "failsafe"). Actual function depends on bootloader configuration. Use a proper binding for that. While at it fix numbers formatting to avoid: arch/arm/boot/dts/bcm47094-linksys-panamera.dt.yaml: partitions: 'partition@1F00000' does not match any of the regexes: '^partition@[0-9a-f]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml Signed-off-by: -
Michael Walle authored
For completeness, add the rtc0 alias. Signed-off-by:
Michael Walle <michael@walle.cc> Signed-off-by:
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Michael Walle authored
The aliases are board-specific and shouldn't be included in the common SoC dtsi. Move them over to the boards. Signed-off-by:
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Michael Walle authored
The failsafe partitions for the DP firmware and for AT-F are unused. If AT-F will ever be supported in the failsafe mode, then it will be a FIT image. Thus fold the unused partitions into the failsafe bootloader one to have enough storage if the bootloader image will grow. While at it, remove the reserved partition. It served no purpose other than having no hole in the map. Signed-off-by:
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Michael Walle authored
Move the MTD partitions to the partitions subnode. This is the new way to specify the partitions, see Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Signed-off-by:
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Fabio Estevam authored
According to the datasheet RTL8211, it must be asserted low for at least 10ms and at least 72ms "for internal circuits settling time" before accessing the PHY registers. Add properties to describe such requirements. Reported-by:
Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by:
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Sebastian Krzyszkowiak authored
Commit 99e71c02 ("arm64: dts: imx8mq-librem5: Don't mark buck3 as always on") removed always-on marking from GPU regulator, which is great for power saving - however it introduces additional i2c0 traffic which can be deadly for devices from the Dogwood batch. To workaround the i2c0 shutdown issue on Dogwood, this commit marks buck3 as always-on again - but only for Dogwood (r3). Signed-off-by:
Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by:
Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by:
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Guido Günther authored
There was an additional alias in the specifier it hogged line 27 instead of line 1. Signed-off-by:
Guido Günther <agx@sigxcpu.org> Signed-off-by:
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Russell King authored
Add 2x2 SFP+ cage support for clearfog-itx boards. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Teresa Remmet authored
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved. Signed-off-by:
Teresa Remmet <t.remmet@phytec.de> Signed-off-by:
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Kuldeep Singh authored
Reorder flexspi clock-names entry to make it compliant with bindings. Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
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Kuldeep Singh authored
Reorder flexspi clock-names entry to make it compliant with bindings. Signed-off-by:
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Vladimir Oltean authored
In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2 and mscc_felix_port4. This link operates at 2.5Gbps and is described as such for the mscc_felix_port4 node. The reason for the discrepancy is a limitation in the PHY library support for fixed-link nodes. Due to the fact that the PHY library registers a software PHY which emulates the clause 22 register map, the drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps. The mscc_felix_port4 node is probed by DSA, which does not use the PHY library directly, but phylink, and phylink has a different representation for fixed-link nodes, one that does not have the limitation of not being able to represent speeds > 1Gbps. Since the enetc driver was converted to phylink too as of commit 71b77a7a ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation has been practically lifted there too, and we can describe the real link speed in the device tree now. Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Adrien Grassein authored
Add the description for ecspi2 support. Signed-off-by:
Adrien Grassein <adrien.grassein@gmail.com> Reviewed-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
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Dong Aisheng authored
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. This patch adds i.MX8QuadMax MEK board support. Note that MX8QM needs a special workaround for TLB flush due to a SoC errata, otherwise there may be random crash if enable both clusters of A72 and A53. As the errata workaround is still not in mainline, so we disable A72 cluster first for MX8QM MEK. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Dong Aisheng authored
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53 proccessor with powerful graphic and multimedia features. It uses the same architecture as MX8QXP, so many SS can be reused. This patch adds i.MX8QuadMax SoC dtsi file. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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