- 29 May, 2023 3 commits
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Srinivas Kandagatla authored
WSA Soundwire controller needs an full reset if clock stop support is not available in slave devices. WSA881x does not support clock stop however WSA883x supports clock stop. Make setting this flag at runtime to address above issue. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20230525133812.30841-5-srinivas.kandagatla@linaro.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Srinivas Kandagatla authored
Sometimes Hard reset does not clear some of the registers, this sometimes results in firing a bus clash interrupt. Add workaround for this during power up sequence, as suggested by hardware manual. Signed-off-by:
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Srinivas Kandagatla authored
Wait for Fifo to be empty before going to suspend or before bank switch happens. Just to make sure that all the reads/writes are done. Signed-off-by:
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- 27 May, 2023 28 commits
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Krzysztof Kozlowski authored
Drop unused members from the driver state container: struct qcom_swrm_ctrl. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230515132000.399745-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Chao Song authored
Start from ACE1.x, DOAISE is added to AC timing control register bit 5, it combines with DOAIS to get effective timing, and has the default value 1. The current code fills DOAIS, DACTQE and DODS bits to a variable initialized to zero, and updates the variable to AC timing control register. With this operation, We change DOAISE to 0, and force a much more aggressive timing. The timing is even unable to form a working waveform on SDA pin on Meteorlake. This patch uses read-modify-write operation for the AC timing control register access, thus makes sure those bits not supposed and intended to change are not touched. Signed-off-by:
Chao Song <chao.song@linux.intel.com> Reviewed-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by:
Rander Wang <rander.wang@intel.com> Signed-off-by:
Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20230515081301.12921-1-yung-chuan.liao@linux.intel.comSigned-off-by:
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Pierre-Louis Bossart authored
The interface is not needed for IPC3 but will be needed for ACE2.x+IPC4 combinations, with the substream information passed as a parameter. Signed-off-by:
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by:
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Pierre-Louis Bossart authored
The interface is not needed for IPC3 solution but will be needed with an updated parameter list for ACE2.x+IPC4 combinations. Signed-off-by:
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Pierre-Louis Bossart authored
The interface is not needed for IPC3 but will be needed for ACE2.x+IPC4 combinations, with the substream information passed as a parameter. Signed-off-by:
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Pierre-Louis Bossart authored
The interface is not needed for IPC3 solutions but will be needed with an updated parameter list for ACE2.x+IPC4 combinations. Signed-off-by:
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Pierre-Louis Bossart authored
An earlier simplification to only pass the direction is no longer suitable, all the ACE2.x HDaudio DMA management relies on access to the substream structure. This patch is an iso-functionality change, the HDaudio DMA parts will be provided separately. Signed-off-by:
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Pierre-Louis Bossart authored
The .pre_ and .post_switch callbacks are mandatory. Signed-off-by:
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Pierre-Louis Bossart authored
Add the abstraction needed to only program the LSDIID registers for the HDaudio extended links. It's perfectly fine to program this register multiple times in case devices lose sync and reattach. Signed-off-by:
Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by:
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Pierre-Louis Bossart authored
When a peripheral reports as ATTACHED, the manager may need to follow a programming sequence, e.g. to assign DMA resources and/or assign a command queue for that peripheral. This patch adds an optional callback, which will be invoked every time the peripheral attaches. This might be overkill in some scenarios, and one could argue that this should be invoked only on the first attachment. The bus does not however track this first attachment with any existing state-mirroring variable, and using dev_num_sticky would not work across suspend-resume cycles. Signed-off-by:
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Pierre-Louis Bossart authored
This is the last callback needed for all bus management routines on new hardware. Same concept as before, just different register. Signed-off-by:
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Pierre-Louis Bossart authored
The WAKEEN and WAKESTS registers were moved to the per-link SHIM_VS area. Signed-off-by:
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Pierre-Louis Bossart authored
The sequences are so far identical, so the abstraction is a bit over-engineered. In time we will simplify if there is no need to special case or work-around programming sequences. Signed-off-by:
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Pierre-Louis Bossart authored
Same functionality as before, but with the registers moved to the HDaudio multi-link area. Signed-off-by:
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Pierre-Louis Bossart authored
The code is similar to the previous implementation, the only difference is that the PDI descriptors are now in different areas. Using common helpers proves tricky with multiple changed registers, workarounds that are no longer necessary. It's simpler to duplicate the intel_register_dai() function rather than try to add multiple levels of abstraction and indirections. Signed-off-by:
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Pierre-Louis Bossart authored
Unlike previous hardware generations, the glue-to-master transition is not managed by software, instead the transitions are managed as part of the power-up/down sequences controlled by SPA/CPA bits. The only thing that's required is to configure the link PHY for 'normal' operation instead of the PHY test mode. Signed-off-by:
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Pierre-Louis Bossart authored
The registers used for multi-link synchronization are no longer in the SHIM but in the HDaudio multi-link capability space. Use helpers to configure the SYNCPRD value, and wait for SYNCPU to change after powering-up. Note that the SYNCPRD value is shared between all sublinks, for obvious reasons if those links are supposed to be synchronized. The value of SYNCPRD is programmed only once for all sublinks. Signed-off-by:
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Pierre-Louis Bossart authored
only power-up/down for now, the frequency is not set. Signed-off-by:
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Pierre-Louis Bossart authored
Add access to registers in SHIM and SHIM_VS (vendor-specific) areas. Signed-off-by:
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Pierre-Louis Bossart authored
Now that the ASoC/SOF/HDAudio parts has retrieved the mutex and set the parameter, we can use it to share the same synchronization across the two domains. Signed-off-by:
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Pierre-Louis Bossart authored
Use new helper and interface to make sure the HDaudio and SoundWire parts use the same mutex when accessing shared registers. Signed-off-by:
Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230515071042.2038-9-yung-chuan.liao@linux.intel.comSigned-off-by:
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Pierre-Louis Bossart authored
In existing Intel/SoundWire systems, all the SoundWire configuration is 'self-contained', with the 'shim_lock' mutex used to protect access to shared registers in multi-link configurations. With the move of part of the SoundWire registers to the HDaudio multi-link structure, we need a unified lock. The hda-mlink implementation provides an 'eml_lock' that is used to protect shared registers such as LCTL and LSYNC, we can pass it to the SoundWire side. There is no issue with possible dangling pointers since the SoundWire auxiliary devices are children of the PCI device, so the 'eml_lock' cannot be removed while the SoundWire side is in use. This patch only adds the interface for now. Signed-off-by:
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Pierre-Louis Bossart authored
The hdac_bus pointer is used to access the extended link information and handle power management. Pass it from the SOF driver down to the auxiliary devices. Signed-off-by:
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Pierre-Louis Bossart authored
Select relevant ip-offset depending on hardware version. This offset is used to access MCP_ or IP_MCP_ registers with a fixed offset. For existing platforms, the offset is exactly zero. Starting with LunarLake, the offset is 0x4000. Signed-off-by:
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Pierre-Louis Bossart authored
The previous settings are not applicable, use a flag to determine what the register layout is. Signed-off-by:
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Pierre-Louis Bossart authored
The register map and programming sequences for the ACE2.x IP are completely different and need to be abstracted with a different set of callbacks. This initial patch adds a new file, follow-up patches will add each required callback. Signed-off-by:
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Pierre-Louis Bossart authored
With the HDaudio extended link integration, the SHIM and IP registers are split in blocks a) SHIM generic registers b) IP registers (same offsets for Cadence IP as before) c) SHIM vendor-specific registers Add offsets and definitions as defined in the hardware specifications. Signed-off-by:
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Pierre-Louis Bossart authored
Add the new enum needed for SoundWire IP selection. The LunarLake PCI descriptors and DSP parts will be added at a later time. Signed-off-by:
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- 08 May, 2023 8 commits
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Charles Keepax authored
It makes sense to have only a single point responsible for ensuring that all currently pending IRQs are handled. The current code in sdw_handle_slave_alerts confusingly splits this process in two. This code will loop until the asserted IRQs are cleared but it will only handle IRQs that were already asserted when it was called. This means the caller must also loop (either manually, or through its IRQ mechanism) until the IRQs are all handled. It makes sense to either do all the looping in sdw_handle_slave_alerts or do no looping there and let the host controller repeatedly call it until things are handled. There are realistically two sensible host controllers, those that will generate an IRQ when the alert status changes and those that will generate an IRQ continuously whilst the alert status is high. The current code will work fine for the second of those systems but not the first with out additional looping in the host controller. Removing the code that filters out new IRQs whilst the handler is running enables both types of host controller to be supported and simplifies the code. The code will still only loop up to SDW_READ_INTR_CLEAR_RETRY times, so it shouldn't be possible for it to get completely stuck handling IRQs forever, and if you are generating IRQs faster than you can handle them you likely have bigger problems anyway. This fixes an issue on the Cadence SoundWire IP, which only generates IRQs on an alert status change, where an alert which arrives whilst another alert is being handled will never be handled and will block all future alerts from being handled. Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by:
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Krzysztof Kozlowski authored
Use consistently only tabs to indent the value in defines. Reviewed-by:
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Krzysztof Kozlowski authored
Add support for Qualcomm Soundwire Controller with a bit different register layout. Reviewed-by:
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Krzysztof Kozlowski authored
Currently the driver supports Qualcomm Soundwire controller versions from v1.3 till v1.7 which mostly have same register layout. With coming Qualcomm Soundwire v2.0, several registers were moved and changed, thus a different register layout will have to be supported. Prepare for this by: 1. Renaming few register defines to indicate v1.3 (earliest supported) version, 2. Add a simple table for mapping register to its offset, 3. Change the code to use the mapping table. Since only few registers differ, this solution seems easier then switching to regmap fields. Reviewed-by:
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Krzysztof Kozlowski authored
The pointer to 'struct qcom_swrm_ctrl' was called sometimes 'swrm' and sometimes 'ctrl' variable. Choose one - 'ctrl' - so the code will be consistent and easier to read. No functional change. Reviewed-by:
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Krzysztof Kozlowski authored
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals. Reviewed-by:
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Krzysztof Kozlowski authored
The port sample interval was always 16-bit, split into low and high bytes. This split was unnecessary, although harmless for older devices because all of them used only lower byte (so values < 0xff). With support for Soundwire controller on Qualcomm SM8550 and its devices, both bytes will be used, thus add a new 'qcom,ports-sinterval' property to allow 16-bit sample intervals. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add compatible for Qualcomm Soundwire v2.0.0 controller, which comes with several differences against v1.7.0 in register layout and more ports (thus increase maxItems of each port-related property to 16). Reviewed-by:
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- 07 May, 2023 1 commit
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Linus Torvalds authored
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