1. 06 Dec, 2016 19 commits
    • Ivan Khoronzhuk's avatar
      net: ethernet: ti: cpsw: fix early budget split · 48e0a83e
      Ivan Khoronzhuk authored
      The budget split function requires the phy speed to be known.
      While ndo open a phy speed identification is postponed till the
      moment link is up. Hence, move it to appropriate callback, when link
      is up.
      Reported-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Fixes: 8feb0a19 ("net: ethernet: ti: cpsw: split tx budget according between channels")
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@linaro.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      48e0a83e
    • Florian Westphal's avatar
      Revert "dctcp: update cwnd on congestion event" · 343dfaa1
      Florian Westphal authored
      Neal Cardwell says:
       If I am reading the code correctly, then I would have two concerns:
       1) Has that been tested? That seems like an extremely dramatic
          decrease in cwnd. For example, if the cwnd is 80, and there are 40
          ACKs, and half the ACKs are ECE marked, then my back-of-the-envelope
          calculations seem to suggest that after just 11 ACKs the cwnd would be
          down to a minimal value of 2 [..]
       2) That seems to contradict another passage in the draft [..] where it
          sazs:
             Just as specified in [RFC3168], DCTCP does not react to congestion
             indications more than once for every window of data.
      
      Neal is right.  Fortunately we don't have to complicate this by testing
      vs. current rtt estimate, we can just revert the patch.
      
      Normal stack already handles this for us: receiving ACKs with ECE
      set causes a call to tcp_enter_cwr(), from there on the ssthresh gets
      adjusted and prr will take care of cwnd adjustment.
      
      Fixes: 47805667 ("dctcp: update cwnd on congestion event")
      Cc: Neal Cardwell <ncardwell@google.com>
      Signed-off-by: default avatarFlorian Westphal <fw@strlen.de>
      Acked-by: default avatarNeal Cardwell <ncardwell@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      343dfaa1
    • David S. Miller's avatar
      Merge branch 'mv88e6xxx-rework-reset-and-PPU-code' · b1df0f5c
      David S. Miller authored
      Vivien Didelot says:
      
      ====================
      net: dsa: mv88e6xxx: rework reset and PPU code
      
      Old Marvell chips (like 88E6060) don't have a PHY Polling Unit (PPU).
      
      Next chips (like 88E6185) have a PPU, which has exclusive access to the
      PHY registers, thus must be disabled before access.
      
      Newer chips (like 88E6352) have an indirect mechanism to access the PHY
      registers whenever, thus loose control over the PPU (always enabled).
      
      Here's a summary:
      
      Model | PPU? | Has PPU ctrl?  | PPU state readable? | PHY access
      ----- | ---- | -------------- | ------------------- | ----------
       6060 | no   | no             | no                  | direct
       6185 | yes  | yes, PPUEn bit | yes, PPUState 2-bit | direct w/ PPU dis.
       6352 | yes  | no             | yes, PPUState 1-bit | indirect
       6390 | yes  | no             | yes, InitState bit  | indirect
      
      Depending on the PPU control, a switch may have to restart the PPU when
      resetting the switch. Once the switch is reset, we must wait for the PPU
      state to be active polling again before accessing the registers.
      
      For that purpose, add new operations to the chips to enable/disable the
      PPU, and execute software reset. With these new ops in place, rework the
      switch reset code and finally get rid of the MV88E6XXX_FLAG_PPU* flags.
      
      Changes in v3:
        - consider 6097 as 6352 (no PPU ops and use mv88e6352_g1_reset).
      
      Changes in v2:
        - wait in ppu/reset ops so that ppu_polling is not needed anymore.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b1df0f5c
    • Vivien Didelot's avatar
      net: dsa: mv88e6xxx: add PPU operations · a199d8b6
      Vivien Didelot authored
      Some Marvell chips can enable/disable the PPU on demand. This is needed
      to access the PHY registers when there is no indirection mechanism.
      
      Add two new ppu_enable and ppu_disable ops to describe this and finally
      get rid of the MV88E6XXX_FLAG_PPU* flags.
      Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a199d8b6
    • Vivien Didelot's avatar
      net: dsa: mv88e6xxx: add a soft reset operation · 17e708ba
      Vivien Didelot authored
      Marvell chips have different way to issue a software reset.
      
      Old chips (such as 88E6060) have a reset bit in an ATU control register.
      
      Newer chips moved this bit in a Global control register. Chips with
      controllable PPU should reset the PPU when resetting the switch.
      
      Add a new reset operation to implement these differences and introduce a
      mv88e6xxx_software_reset() helper to wrap it conveniently.
      Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      17e708ba
    • Vivien Didelot's avatar
      net: dsa: mv88e6xxx: add helper to hardware reset · 309eca6d
      Vivien Didelot authored
      Add an helper to toggle the eventual GPIO connected to the reset pin.
      Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      309eca6d
    • Vivien Didelot's avatar
      net: dsa: mv88e6xxx: add helper to disable ports · 4ac4b5a6
      Vivien Didelot authored
      Before resetting a switch, the ports should be set to the Disabled state
      and the transmit queues should be drained.
      
      Add an helper to explicit that.
      Signed-off-by: default avatarVivien Didelot <vivien.didelot@savoirfairelinux.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4ac4b5a6
    • David S. Miller's avatar
      Merge branch 'Alacritech-SLIC-driver' · 9f9ffdff
      David S. Miller authored
      Lino Sanfilippo says:
      
      ====================
      Gigabit ethernet driver for Alacritechs SLIC devices (v4)
      
      this is the forth version of the slicoss gigabit ethernet driver (which is a
      rework of the driver from Alacritech which can currently be found under
      drivers/staging/slicoss). The driver is supposed to support Mojave, Oasis and
      Kalahari cards, for both copper and fiber.
      
      If this code is accepted the staging version can be removed.
      
      The driver has been tested on a SEN2104ET adapter (4 Port PCIe copper).
      
      v4:
      - fix wrong driver name in Kconfig file (reported by Rami Rosen)
      - remove unused variable from driver struct (reported by Rami Rosen)
      - return "err" instead of 0 in slic_load_rcvseq_firmware() (reported by Rami Rosen)
      - Fix typos in constants, comments and error message (reported by Markus Böhme)
      - fix various warnings concerning signedness (reported by Markus Böhme)
      - improve line formatting (reported by Markus Böhme)
      - add comment describing the need for SLIC_MAX_TX_COMPLETIONS (suggested by Florian Fainelli)
      - do not zero out complete rx descriptor (suggested by Florian Fainelli)
      - add missing write barrier (reported by Florian Fainelli)
      - remove unneeded assignment of net_device to skb (reported by Florian Fainelli)
      - use napi_complete_done() instead of napi_complete (suggested by Florian Fainelli)
      - use napi_schedule_irqoff() instead of napi_schedule (suggested by Florian Fainelli)
      - do not map error returned by slic_init() to -ENOMEM
      - do proper dma syncs before and after rx descriptor status is set to 0
      - if after dma sync for CPU rx descriptor is not used return it to HW by means of dma sync for device
      
      v3:
      - dont add defines to pci_ids.h but instead put it into the drivers header file
      (requested by Greg Kroah-Hartman)
      
      v2:
      - remove unusual padding in statistic strings (suggested by Andrew Lunn)
      - for mdio register and bit names use defines from mii.h instead of own ones
        (suggested by Andrew Lunn)
      - remove unused defines
      - ensure PCI flush at two more places
      - use mmiowb before lock to prevent mmio writes leaking out of lock
      - fix some typos in comments
      - add copyright and GPL header
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9f9ffdff
    • Lino Sanfilippo's avatar
      MAINTAINERS: add entry for slicoss ethernet driver · b9567027
      Lino Sanfilippo authored
      Add myself as maintainer for the slicoss ethernet driver.
      Signed-off-by: default avatarLino Sanfilippo <LinoSanfilippo@gmx.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b9567027
    • Lino Sanfilippo's avatar
      net: ethernet: slicoss: add slicoss gigabit ethernet driver · 60c140df
      Lino Sanfilippo authored
      Add driver for Alacritech gigabit ethernet cards with SLIC (session-layer
      interface control) technology. The driver provides basic support without
      SLIC for the following devices:
      
      - Mojave cards (single port PCI Gigabit) both copper and fiber
      - Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
      - Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
      Signed-off-by: default avatarLino Sanfilippo <LinoSanfilippo@gmx.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      60c140df
    • Eric Dumazet's avatar
      net/udp: do not touch skb->peeked unless really needed · a297569f
      Eric Dumazet authored
      In UDP recvmsg() path we currently access 3 cache lines from an skb
      while holding receive queue lock, plus another one if packet is
      dequeued, since we need to change skb->next->prev
      
      1st cache line (contains ->next/prev pointers, offsets 0x00 and 0x08)
      2nd cache line (skb->len & skb->peeked, offsets 0x80 and 0x8e)
      3rd cache line (skb->truesize/users, offsets 0xe0 and 0xe4)
      
      skb->peeked is only needed to make sure 0-length packets are properly
      handled while MSG_PEEK is operated.
      
      I had first the intent to remove skb->peeked but the "MSG_PEEK at
      non-zero offset" support added by Sam Kumar makes this not possible.
      
      This patch avoids one cache line miss during the locked section, when
      skb->len and skb->peeked do not have to be read.
      
      It also avoids the skb_set_peeked() cost for non empty UDP datagrams.
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Acked-by: default avatarPaolo Abeni <pabeni@redhat.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a297569f
    • David S. Miller's avatar
      Merge branch 'hix5hd2_gmac-txsg-reset-clock-control' · e466af66
      David S. Miller authored
      Dongpo Li says:
      
      ====================
      net: hix5hd2_gmac: add tx sg feature and reset/clock control signals
      
      The "hix5hd2" is SoC name, add the generic ethernet driver compatible string.
      The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
      the SG/TXCSUM/TSO/UFO features.
      This patch set only adds the SG(scatter-gather) driver for transmitting,
      the drivers of other features will be submitted later.
      
      Add the MAC reset control signals and clock signals.
      We make these signals optional to be backward compatible with
      the hix5hd2 SoC.
      
      Changes in v2:
      - Make the compatible string changes be a separate patch and
      the most specific string come first than the generic string
      as advised by Rob.
      - Make the MAC reset control signals and clock signals optional
      to be backward compatible with the hix5hd2 SoC.
      - Change the compatible string and give the clock a specific name
      in hix5hd2 dts file.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e466af66
    • Dongpo Li's avatar
      ARM: dts: hix5hd2: add gmac generic compatible and clock names · 0855950b
      Dongpo Li authored
      Add gmac generic compatible and clock names.
      Signed-off-by: default avatarDongpo Li <lidongpo@hisilicon.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0855950b
    • Dongpo Li's avatar
      net: hix5hd2_gmac: add reset control and clock signals · 7087140d
      Dongpo Li authored
      Add three reset control signals, "mac_core_rst", "mac_ifc_rst" and
      "phy_rst".
      The following diagram explained how the reset signals work.
      
                              SoC
      |-----------------------------------------------------
      |                               ------                |
      |                               | cpu |               |
      |                               ------                |
      |                                  |                  |
      |                              ------------ AMBA bus  |
      |                         GMAC     |                  |
      |                            ----------------------   |
      | ------------- mac_core_rst | --------------      |  |
      | |clock and   |-------------->|   mac core  |     |  |
      | |reset       |             | --------------      |  |
      | |generator   |----         |       |             |  |
      | -------------     |        | ----------------    |  |
      |          |        ---------->| mac interface |   |  |
      |          |     mac_ifc_rst | ----------------    |  |
      |          |                 |       |             |  |
      |          |                 | ------------------  |  |
      |          |phy_rst          | | RGMII interface | |  |
      |          |                 | ------------------  |  |
      |          |                 ----------------------   |
      |----------|------------------------------------------|
                 |                          |
                 |                      ----------
                 |--------------------- |PHY chip |
                                        ----------
      
      The "mac_core_rst" represents "mac core reset signal", it resets
      the mac core including packet processing unit, descriptor processing unit,
      tx engine, rx engine, control unit.
      The "mac_ifc_rst" represents "mac interface reset signal", it resets
      the mac interface. The mac interface unit connects mac core and
      data interface like MII/RMII/RGMII. After we set a new value of
      interface mode, we must reset mac interface to reload the new mode value.
      The "mac_core_rst" and "mac_ifc_rst" are both optional to be
      backward compatible with the hix5hd2 SoC.
      The "phy_rst" represents "phy reset signal", it does a hardware reset
      on the PHY chip. This reset signal is optional if the PHY can work well
      without the hardware reset.
      
      Add one more clock signal, the existing is MAC core clock,
      and the new one is MAC interface clock.
      The MAC interface clock is optional to be backward compatible with
      the hix5hd2 SoC.
      Signed-off-by: default avatarDongpo Li <lidongpo@hisilicon.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7087140d
    • Dongpo Li's avatar
      net: hix5hd2_gmac: add tx scatter-gather feature · e5222b1c
      Dongpo Li authored
      "hisi-gemac-v2" adds the SG/TXCSUM/TSO/UFO features.
      This patch only adds the SG(scatter-gather) driver for transmitting,
      the drivers of other features will be submitted later.
      Signed-off-by: default avatarDongpo Li <lidongpo@hisilicon.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e5222b1c
    • Dongpo Li's avatar
      net: hix5hd2_gmac: add generic compatible string · d0fb6ba7
      Dongpo Li authored
      The "hix5hd2" is SoC name, add the generic ethernet driver name.
      The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
      the SG/TXCSUM/TSO/UFO features.
      Signed-off-by: default avatarDongpo Li <lidongpo@hisilicon.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d0fb6ba7
    • Stefan Eichenberger's avatar
      net: dsa: mv88e6xxx: Use EDSA on mv88e6097 · 2bfcfcd3
      Stefan Eichenberger authored
      Use DSA_TAG_PROTO_EDSA as tag_protocol for the mv88e6097. The
      initialisation was missing before.
      
      Fixes: a1f482aa8c33 ("net: dsa: mv88e6xxx: Move the tagging protocol into info")
      Signed-off-by: default avatarStefan Eichenberger <stefan.eichenberger@netmodule.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2bfcfcd3
    • Thomas Graf's avatar
      bpf: add additional verifier tests for BPF_PROG_TYPE_LWT_* · 3f731d89
      Thomas Graf authored
      - direct packet read is allowed for LWT_*
       - direct packet write for LWT_IN/LWT_OUT is prohibited
       - direct packet write for LWT_XMIT is allowed
       - access to skb->tc_classid is prohibited for LWT_*
      Signed-off-by: default avatarThomas Graf <tgraf@suug.ch>
      Acked-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
      Acked-by: default avatarAlexei Starovoitov <ast@kernel.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3f731d89
    • Haiyang Zhang's avatar
      tools: hv: Enable network manager for bonding scripts on RHEL · fd7aabb0
      Haiyang Zhang authored
      We found network manager is necessary on RHEL to make the synthetic
      NIC, VF NIC bonding operations handled automatically. So, enabling
      network manager here.
      Signed-off-by: default avatarHaiyang Zhang <haiyangz@microsoft.com>
      Reviewed-by: default avatarK. Y. Srinivasan <kys@microsoft.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fd7aabb0
  2. 05 Dec, 2016 21 commits