- 10 Feb, 2023 16 commits
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Abel Vesa authored
Add SM8550 specific register layout and table configs. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
Add the SM8550 compatible to the list. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Abel Vesa authored
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by:
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Abel Vesa authored
The SM8550 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema for the new driver. Signed-off-by:
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Abel Vesa authored
Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
Document the QMP PCIe PHY compatible for SM8550. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Neil Armstrong authored
Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by:
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Neil Armstrong authored
Document the USB3/DP Combo PHY compatible found on the SM8350 & SM8450 SoCs. Signed-off-by:
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- 03 Feb, 2023 11 commits
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Stephen Boyd authored
Introduce a config option for each QMP PHY driver now that the QMP PHY mega-driver has been split up into different modules. This allows kernel configurators to limit the binary size of the kernel by only compiling in the QMP PHY driver that they need. Leave the old config QCOM_QMP in place and make it into a menuconfig so that 'make olddefconfig' continues to work. Furthermore, set the default of the new Kconfig symbols to be QCOM_QMP so that the transition is smooth. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.orgSigned-off-by:
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Jon Hunter authored
Add the compatible string for the Tegra234 XUSB PHY. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
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Vinod Koul authored
Merge tag phy-devm_of_phy_optional_get into next to bring in the new devm_of_phy_optional_get() API and users
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Geert Uytterhoeven authored
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. This lets us drop several checks for IS_ERR(), as phy_power_{on,off}() handle NULL parameters fine. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Alan Stern <stern@rowland.harvard.edu> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/3adc5dd1149a17ea7daf4463549feab886c6b145.1674584626.git.geert+renesas@glider.beSigned-off-by:
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Geert Uytterhoeven authored
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. This lets us drop several checks for IS_ERR(), as phy_power_{on,off}() handle NULL parameters fine. Signed-off-by: -
Geert Uytterhoeven authored
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/56508eeadf7fa8692877e872871f10294d48c49d.1674584626.git.geert+renesas@glider.beSigned-off-by:
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Geert Uytterhoeven authored
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. Signed-off-by:
Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/993b0f4ac5b84b2b72223011614d2e821f9e7302.1674584626.git.geert+renesas@glider.beSigned-off-by:
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Geert Uytterhoeven authored
Use the new devm_of_phy_optional_get() helper instead of open-coding the same operation. As devm_of_phy_optional_get() returns NULL if either the PHY cannot be found, or if support for the PHY framework is not enabled, it is no longer needed to check for -ENODEV or -ENOSYS. Signed-off-by:
Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/f2d801cd73cca36a7162819289480d7fc91fcc7e.1674584626.git.geert+renesas@glider.beSigned-off-by:
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Geert Uytterhoeven authored
Add an optional variant of devm_of_phy_get() that also takes care of printing real errors, so drivers no longer have to open-code this operation. Signed-off-by:
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Geert Uytterhoeven authored
Add the missing documentation for devm_of_phy_get(), which was forgotten when the function was introduced. Signed-off-by:
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Geert Uytterhoeven authored
There were never any upstream users of this function since its introduction almost 10 years ago. Besides, the dummy for phy_optional_get() should have returned NULL instead of an error code. Signed-off-by:
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- 02 Feb, 2023 9 commits
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Luca Weiss authored
Add the tables and config for the combo phy found on SM6350. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Luca Weiss authored
Add the compatible describing the combo phy found on SM6350. Reviewed-by:
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Chunfeng Yun authored
Remove the temporary @mask_, this may cause build warning when use clang compiler for powerpc, but can't reproduce it when compile for arm64. the build warning is caused by: "warning: result of comparison of constant 18446744073709551615 with expression of type (aka 'unsigned long') is always false [-Wtautological-constant-out-of-range-compare]" More information provided in below lore link. After removing @mask_, there is a "CHECK:MACRO_ARG_REUSE" when run checkpatch.pl, but due to @mask is constant, no reuse problem will happen. Link: https://lore.kernel.org/lkml/202212160357.jJuesD8n-lkp@intel.com/t/ Fixes: 84513ecc ("phy: mediatek: fix build warning of FIELD_PREP()") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118084343.26913-1-chunfeng.yun@mediatek.comSigned-off-by:
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Abel Vesa authored
Add SM8550 specific register layout and table configs. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes TX RX offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by:
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Abel Vesa authored
Document the QMP UFS PHY compatible for SM8550. Signed-off-by:
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- 31 Jan, 2023 1 commit
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Geert Uytterhoeven authored
The NXP TJR1443 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1043. Signed-off-by:
Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/0bfa1e4c43632e49c9512b4e7daa970545545dcf.1674037830.git.geert+renesas@glider.beSigned-off-by:
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- 20 Jan, 2023 1 commit
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Geert Uytterhoeven authored
The NXP TJR1443 High-speed CAN transceiver with Sleep mode is a pin-compatible alternative for the TI TCAN1043. Signed-off-by:
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- 18 Jan, 2023 2 commits
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Thierry Reding authored
Convert the Tegra XUSB pad controller bindings from free-form text format to json-schema. Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230113150804.1272555-1-thierry.reding@gmail.comSigned-off-by:
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Dmitry Baryshkov authored
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout while the PHY itself uses v5 regs. While there are only minor differences between v4 and v5 regs and none of them concerns registers mentions in regs_layout, switch the PHY to use qmp_v5_usb3phy_regs_layout, to remove possible confusion. Fixes: 14d98d3b ("phy: qcom-qmp-usb: fix regs layout arrays") Signed-off-by:
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