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- 25 Jul, 2023 1 commit
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Biju Das authored
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow interrupt names start with 'tci' instead of 'tgi'. Replace the below overflow/underflow interrupt names: - tgiv0->tciv0 - tgiv1->tciv1 - tgiu1->tciu1 - tgiv2->tciv2 - tgiu2->tciu2 - tgiv3->tciv3 - tgiv4->tciv4 - tgiv6->tciv6 - tgiv7->tciv7 - tgiv8->tciv8 - tgiu8->tciu8 Fixes: 26336d66 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") Fixes: dd123dd0 ("arm64: dts: renesas: r9a07g054: Add MTU3a node") Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230724091927.123847-5-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 May, 2023 4 commits
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Biju Das authored
Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230417090159.191346-1-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add DSI node to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-6-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add vspd node to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add fcpvd node to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 30 Mar, 2023 2 commits
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Lad Prabhakar authored
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 10 Mar, 2023 1 commit
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Lad Prabhakar authored
From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a34131 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 06 Mar, 2023 2 commits
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Lad Prabhakar authored
The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L (r9a07g044) SoC. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 Nov, 2022 2 commits
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Lad Prabhakar authored
This fixes the below dtbs_check warning: arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml Drop #address-cells properties from pinctrl nodes as they have no addressed child nodes. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221107172953.63218-1-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20221107172953.63218-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Pierre Gondois authored
The DeviceTree Specification v0.3 specifies that the cache node 'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes. Update the Device Trees accordingly. Signed-off-by:
Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com [geert: Update description] Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 17 Oct, 2022 1 commit
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Lad Prabhakar authored
On members of the RZ/G2L family, WDT CH2 is specifically meant to check the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU would result in unexpected behaviour. Hence drop all WDT2 nodes and their references from the affected SoC and SoM DTSI files. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 19 Sep, 2022 1 commit
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Lad Prabhakar authored
Drop extra space around the '{' sign. No functional changes (same DTB). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 22 Aug, 2022 2 commits
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Biju Das authored
As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Fixes: f9a2adcc ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes") Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add DMA properties to RSPI nodes to support DMA operation. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220728122312.189766-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 15 Aug, 2022 2 commits
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Lad Prabhakar authored
Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220718195651.7711-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220718195651.7711-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 06 May, 2022 1 commit
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Biju Das authored
Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 17 Dec, 2021 1 commit
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Geert Uytterhoeven authored
Align all pin controller node names with the expectations of the DT bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
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- 16 Dec, 2021 1 commit
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Biju Das authored
Add Mali-G31 GPU node to SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 14 Dec, 2021 2 commits
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Biju Das authored
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham <dien.pham.ry@renesas.com> and others for r8a77990 SoC. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add TSU node to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 26 Nov, 2021 5 commits
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Biju Das authored
Add OPP table for RZ/G2L SoC. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Rename the below SDHI clocks to match with the clocks used in driver. imclk->core clk_hs->clkh imclk2->cd Also re-arrange the clocks to match with the sorting order used in the binding document. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Sort psci node alphabetically. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211112081003.15453-4-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 19 Nov, 2021 1 commit
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Lad Prabhakar authored
Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211117011247.27621-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 15 Nov, 2021 2 commits
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Lad Prabhakar authored
Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 14 Oct, 2021 1 commit
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Biju Das authored
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211013075647.32231-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 08 Oct, 2021 2 commits
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Biju Das authored
Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211007155451.10654-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored
Add SPI Multi I/O Bus controller node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928155852.32569-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 24 Sep, 2021 1 commit
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Biju Das authored
Add dmac phandles to SSI nodes to support DMA operation. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210921084605.16250-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 20 Sep, 2021 5 commits
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Biju Das authored
Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210814135526.15561-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI. The external audio clocks are configured as 0 Hz fixed frequency clocks by default. Boards that provide audio clocks should override them. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210814135526.15561-2-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add USB2.0 device support to RZ/G2L SoC DT. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210812151808.7916-4-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add USB2.0 phy and host support to SoC DT. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210812151808.7916-3-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Biju Das authored
Add DMAC support to RZ/G2L SoC DT. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210719092535.4474-4-biju.das.jz@bp.renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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