- 03 Apr, 2020 3 commits
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Stephen Boyd authored
Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-next - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers * clk-ti: clk: keystone: Add new driver to handle syscon based clocks dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK * clk-ingenic: clk: ingenic/TCU: Fix round_rate returning error clk: ingenic/jz4770: Exit with error if CGU init failed clk: JZ4780: Add function for enable the second core. clk: Ingenic: Add support for TCU of X1000. * clk-typo: clk: Fix trivia typo in comment exlusive => exclusive * clk-at91: clk: at91: add at91rm9200 pmc driver clk: at91: add at91sam9n12 pmc driver clk: at91: add sama5d3 pmc driver clk: at91: add at91sam9g45 pmc driver clk: at91: usb: introduce num_parents in driver's structure clk: at91: usb: use proper usbs_mask clk: at91: sam9x60: fix usb clock parents clk: at91: usb: continue if clk_hw_round_rate() return zero clk: at91: sam9x60: Don't use audio PLL * clk-mmp2: clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks clk: mmp2: Add PLLs that are available on MMP3 dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs clk: mmp2: Check for MMP3 dt-bindings: clock: Add MMP3 compatible string clk: mmp2: Stop pretending PLL outputs are constant clk: mmp2: Add support for PLL clock sources dt-bindings: clock: Convert marvell,mmp2-clock to json-schema clk: mmp2: Constify some strings clk: mmp2: Remove a unused prototype * clk-arm-icst: MAINTAINERS: dt: update reference for arm-integrator.txt clk: versatile: Add device tree probing for IM-PD1 clocks clk: versatile: Export icst_clk_setup() dt-bindings: clock: Create YAML schema for ICST clocks
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Stephen Boyd authored
- Don't show clk phase when it is invalid * clk-phase-errors: clk: rockchip: fix mmc get phase clk: Fix phase init check clk: Bail out when calculating phase fails during clk registration clk: Move rate and accuracy recalc to mostly consumer APIs clk: Use 'parent' to shorten lines in __clk_core_init() clk: Don't cache errors from clk_ops::get_phase() * clk-amlogic: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate * clk-renesas: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks * clk-allwinner: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
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Stephen Boyd authored
* clk-samsung: clk: samsung: Remove redundant check in samsung_cmu_register_one * clk-formatting: clk: Fix continuation of of_clk_detect_critical() * clk-si5341: clk, clk-si5341: Support multiple input ports * clk-socfpga: clk: socfpga: stratix10: simplify parameter passing clk: stratix10: use do_div() for 64-bit calculation
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- 25 Mar, 2020 1 commit
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Mauro Carvalho Chehab authored
This file was renamed. Update references accordingly. Fixes: 78c7d8f9 ("dt-bindings: clock: Create YAML schema for ICST clocks") Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lkml.kernel.org/r/491d2928a47f59da3636bc63103a5f63fec72b1a.1584966325.git.mchehab+huawei@kernel.orgAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 21 Mar, 2020 27 commits
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Lubomir Rintel authored
They were reversed because I read the datasheet upside down. Actually there is no datasheet, but I ended up understanding the comments in Open Firmware driver wrong. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.skSigned-off-by:
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Lubomir Rintel authored
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by:
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Lubomir Rintel authored
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by:
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Lubomir Rintel authored
The register definitions gotten from OLPC Open Firmware. Signed-off-by:
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Lubomir Rintel authored
There seems to be a single thermal sensor block on MMP2 and a couple more on MMP3. Add definitions for their respective clocks. Signed-off-by:
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Lubomir Rintel authored
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Meaning of the relevant APMU_GPU bits were gotten from James Cameron's message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree. [1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html [2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=8ce9f6122Signed-off-by:
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Lubomir Rintel authored
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Signed-off-by:
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Lubomir Rintel authored
There are more PLLs on MMP3 and are configured slightly differently. Tested on a MMP3-based Dell Wyse 3020 machine. Signed-off-by:
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Lubomir Rintel authored
MMP3 variant provides some more clocks. Add respective IDs. Signed-off-by:
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Lubomir Rintel authored
The MMP3's are similar enough to MMP2, but there are differencies, such are more clocks available on the newer model. We want to tell which platform are we on. Signed-off-by:
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Lubomir Rintel authored
This binding describes the PMUs that are found on MMP3 as well. Add the compatible strings and adjust the description. Signed-off-by:
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Lubomir Rintel authored
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also configurable. Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and set-pll2-988mhz Open Firmware words. Signed-off-by:
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Lubomir Rintel authored
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable. Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c A separate commit will adjust the clk-of-mmp2 driver. Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop. Signed-off-by:
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Lubomir Rintel authored
Convert the fixed-factor-clock binding to DT schema format using json-schema. While at that, fix a couple of small errors: make the file base name match the compatible string, add an example and document the reg-names property. Signed-off-by:
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Lubomir Rintel authored
All the parent clock names for the muxes are constant. Add const. Signed-off-by:
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Lubomir Rintel authored
There is no mmp_clk_register_pll2() routine. Signed-off-by:
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Alexandre Belloni authored
Add a driver for the PMC clocks of the at91rm9200. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.comSigned-off-by:
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Linus Walleij authored
As we want to move these clocks over to probe from the device tree we add a device tree probing path. The old platform data path will be deleted once we have the device tree overall code in place. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-3-linus.walleij@linaro.orgSigned-off-by:
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Linus Walleij authored
Export this clock setup method so we can register the IM-PD1 clocks with common code in the next step. Signed-off-by:
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Linus Walleij authored
The ICST clocks used in the ARM Integrator, Versatile and RealView platforms are updated to use YAML schema, and two new ICST clocks used by the Integrator IM-PD1 logical module are added in the process. Cc: devicetree@vger.kernel.org Reviewed-by:
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Andy Shevchenko authored
Fix trivia typo in comment exlusive => exclusive. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lkml.kernel.org/r/20200310135507.87959-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Paul Cercueil authored
When requesting a rate superior to the parent's rate, it would return -EINVAL instead of simply returning the parent's rate like it should. Fixes: 4f89e4b8 ("clk: ingenic: Add driver for the TCU clocks") Cc: stable@vger.kernel.org Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.netSigned-off-by:
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Paul Cercueil authored
Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: 7a01c190 ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by:
kbuild test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.netSigned-off-by:
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Vignesh Raghavendra authored
On TI's AM654/J721e SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control Module registers. Sometime more than one clock control can be in the same register. Add a driver to support such clocks using syscon framework. Driver currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654 SoC. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Link: https://lkml.kernel.org/r/20200227053529.16479-3-vigneshr@ti.comSigned-off-by:
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Vignesh Raghavendra authored
Add DT bindings for TI EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by:
H. Nikolaus Schaller <hns@goldelico.com> Tested-by:
Paul Boddie <paul@boddie.org.uk> Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
X1000 has a different TCU, since X1000 OST has been independent of TCU. This patch is add TCU support of X1000, and prepare for later OST driver. Signed-off-by:
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- 16 Mar, 2020 2 commits
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Chen-Yu Tsai: Changes consist mainly of cleanups for the display engine clock driver, correcting clocks that don't exist. Also, the MBUS clock on the A64 is exported for the device tree to consume. * tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Improved clock/reset handling for the R-Car USB2 Clock Selector - Conversion to json-schema of the Renesas CPG/MSSR DT bindings * tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
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- 11 Mar, 2020 1 commit
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Geert Uytterhoeven authored
Convert the Renesas Clock Pulse Generator / Module Standby and Software Reset Device Tree binding documentation to json-schema. Note that #reset-cells was incorrecty marked a required property for RZ/A2 before. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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- 09 Mar, 2020 4 commits
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Yoshihiro Shimoda authored
This hardware needs to deassert resets of both host and peripheral. So, this patch adds reset control. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.comSigned-off-by:
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Yoshihiro Shimoda authored
This hardware needs to enable clocks of both host and peripheral. So, this patch adds multiple clocks management. Signed-off-by:
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Yoshihiro Shimoda authored
This patch adds missing required properties of power-domains and resets. Fortunately, no one has this device node for now, so that we don't need to think of backward compatibility. Fixes: 311accb6 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY") Signed-off-by:
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Yoshihiro Shimoda authored
Since the hardware requires to enable both USB 2.0 host and peripheral functional clock, this patch fixes the documentation. Fortunately, no one has this device node for now, so that we don't need to think of backward compatibility. Fixes: 311accb6 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY") Signed-off-by:
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- 06 Mar, 2020 2 commits
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull Amlogic clk driver updates from Jerome Brunet: - Update audio clock gate hierarchy for meson8 and gxbb - Update g12a spicc clock sources * tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3 - Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N * tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks
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