- 30 Jan, 2024 5 commits
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Bryan O'Donoghue authored
Add CAMSS block definition for sc8280xp. This drop contains definitions for the following components on sc8280xp: VFE * 4 VFE Lite * 4 CSID * 4 CSIPHY * 4 This dtsi definition has been developed and validated on a Lenovo X13s laptop. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-4-cdd5c57ff1dc@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Bryan O'Donoghue authored
sc8280xp has four Camera Control Interface (CCI) blocks which pinout to two I2C master controllers for each CCI. The CCI I2C pins are not muxed so we define them in the dtsi. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Bjorn Andersson authored
With the necessary support in place for supplying VDD_GFX from the MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU and the GPU on the SA8295P ADP. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-7-7011c2a63037@quicinc.comSigned-off-by:
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Bjorn Andersson authored
The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the bus. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Bjorn Andersson authored
The SA8295P and SA8540P uses an external regulator (max20411), and gfx.lvl is not provided by rpmh. Drop the power-domains property of the gpucc node to reflect this. Fixes: eec51ab2 ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") Reviewed-by:
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- 28 Jan, 2024 16 commits
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Luca Weiss authored
Specify the file name for the squashed/non-split firmware with the .mbn extension instead of the split .mdt. The kernel can load both but the squashed version is preferred in dts nowadays. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Dmitry Baryshkov authored
It seems, the only actual mentions of PM2250 can be found are related to the Qualcomm RB1 platform. However even RB1 schematics use PM4125 as a PMIC name. Rename PM2250 to PM4125 to follow the documentation. Note, this doesn't change the compatible strings. There was a previous argument regarding renaming of compat strings. Fixes: c309b9a5 ("arm64: dts: qcom: Add initial PM2250 device tree") Acked-by:
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Luca Weiss authored
Via the PMIC GLINK driver we can get info about fuel gauge, charger and USB connector events. Add the node to the dts and configure USB so that role switching works. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20231220-fp5-pmic-glink-v1-3-2a1f8e3c661c@fairphone.comSigned-off-by:
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David Heidelberg authored
Make it easier to understand what the reg in those nodes is by using the constants provided by qcom,q6dsp-lpass-ports.h. Name nodes according to dt-binding expectations. Fix for ``` arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb: service@4: dais: Unevaluated properties are not allowed ('qi2s@22', 'qi2s@23' were unexpected) ``` Fixes: b7b73428 ("arm64: dts: qcom: sdm845-oneplus-*: add audio devices") Signed-off-by:David Heidelberg <david@ixit.cz> Reviewed-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231229200245.259689-1-david@ixit.czSigned-off-by:
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Luca Weiss authored
It seems we also need to reserve a region of 81 MiB called "removed_mem" otherwise we can easily hit the following error with higher RAM usage: [ 1467.809274] Internal error: synchronous external abort: 0000000096000010 [#2] SMP Fixes: eee9602a ("arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5") Signed-off-by:
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Luca Weiss authored
When the properties num-channels & qcom,num-ees are not specified, the driver tries to read the values from registers, but this read fails and resets the device if the interconnect from the qcom,qce node is not already active when that happens. Add the static properties to not touch any registers during probe, the rest of the time when the BAM is used by QCE then the interconnect will be active already. Fixes: d488f903 ("arm64: dts: qcom: sc7280: add QCrypto nodes") Signed-off-by:
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Suraj Jaiswal authored
Add changes to support safety IRQ handling support for ethernet. Signed-off-by:
Suraj Jaiswal <quic_jsuraj@quicinc.com> Reviewed-by:
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Stephan Gerhold authored
Add "regulator" to the node names of the fixed regulators, and drop the "_rear" part of the camera node name since it is not part of the class of the device (which is simply "camera"). Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
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Krzysztof Kozlowski authored
Other PCIe nodes in SM8250 and SM8350 have one interrupt name per line, so adjust PCIe0 to match the style. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
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Konrad Dybcio authored
The serial ports did not have their interconnect paths specified when they were first introduced. Fix that. Fixes: 5188049c ("arm64: dts: qcom: Add base SM8450 DTSI") Fixes: f5837418 ("arm64: dts: qcom: sm8450: add uart20 node") Reported-by:
Georgi Djakov <djakov@kernel.org> Signed-off-by:
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- 27 Jan, 2024 19 commits
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Raymond Hackley authored
Document the new following device tree bindings used in their device trees: - samsung,fortuna3g - samsung,gprimeltecan - samsung,grandprimelte - samsung,rossa Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240120095715.13689-2-raymondhackley@protonmail.comSigned-off-by:
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Krzysztof Kozlowski authored
Due to lack of documentation the AMIC4 and AMIC5 analogue microphones were never actually working, so the audio routing for them was added hoping it is correct. It turned out not correct - their routing should point to SWR_INPUT0 (so audio mixer TX SMIC MUX0 = SWR_MIC0) and SWR_INPUT1 (so audio mixer TX SMIC MUX0 = SWR_MIC1), respectively. With proper mixer settings and fixed LPASS TX macr codec TX SMIC MUXn widgets, this makes all microphones working on HDK8450. Cc: stable@vger.kernel.org Fixes: f20cf2bc ("arm64: dts: qcom: sm8450-hdk: add other analogue microphones") Signed-off-by:
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Krzysztof Kozlowski authored
The PCIe nodes should get the ref clock, according to information from Qualcomm. Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, unify the naming scheme of the thermal zones across the tree while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
If the GPU ever reaches this temperature, the "critical" signal shuold definitely be propagated. Fix the wrong type. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
The RPMh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being committed. Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Previous Qualcomm SoCs over the past couple years have used the Arm DSU architecture, which basically unified the meaning of the "cluster" and "system". This is however clearly not the case on X1E, as can be seen by three separate cluster power domains. Add the lacking system-level power domain. For now it's going to be always-on, as no system-wide idle states are defined at the moment. Signed-off-by:
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Krishna Kurapati authored
For qcs404 and ipq5332, certain interrupts are missing in DT. Add them to ensure they are in accordance to bindings. The interrupts added enable remote wakeup functionality for these SoCs. Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-5-quic_kriskura@quicinc.comSigned-off-by:
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Krishna Kurapati authored
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Also modify order of interrupts in accordance to bindings update. Modifying the order of these interrupts is harmless as the driver tries to get these interrupts from DT by name and not by index. Signed-off-by:
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