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- 16 Apr, 2018 5 commits
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Simon Horman authored
Sort the subnodes of the soc node to improve maintainability. The sort has been done alphabetically with the node name as the key. This patch should not introduce any functional change. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Simon Horman authored
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. As per updates for R-Car Gen2 SoCs by Geert Uytterhoeven. Signed-off-by:
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Simon Horman authored
Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together and sorted alphabetically. This patch should not introduce any functional change. Signed-off-by:
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Simon Horman authored
Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3 and Gen2 SoCs in mainline. It is intended to migrate other Renesas ARM-based SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by:
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Chris Brandt authored
Add USB device support. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Reviewed-by:
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- 09 Jan, 2018 2 commits
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Greg Kroah-Hartman authored
This reverts commit 8a99b6ad. Geert doesn't want it going in through the USB tree, ok, whatever... Cc: Chris Brandt <chris.brandt@renesas.com> Reported-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Chris Brandt authored
Add USB device support. Signed-off-by:
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- 16 Oct, 2017 1 commit
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Geert Uytterhoeven authored
Improve hardware description by adding a clock property to the device node corresponding to the CA9 CPU core. Signed-off-by:
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- 31 Jul, 2017 1 commit
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Jacopo Mondi authored
Add pin controller node with 12 gpio controller sub-nodes to r7s72100 dtsi. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
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- 15 May, 2017 1 commit
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Chris Brandt authored
This adds the USB0 and USB1 clocks to the device tree. Signed-off-by:
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- 04 Apr, 2017 3 commits
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Chris Brandt authored
Add the realtime clock device node. Signed-off-by:
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Chris Brandt authored
Add the RTC clocks to device tree. The frequencies must be fixed values according to the hardware manual. Signed-off-by:
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Chris Brandt authored
Add the realtime clock functional clock source. Signed-off-by:
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- 03 Apr, 2017 1 commit
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Chris Brandt authored
Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not the 33MHz Peripheral 0 (P0) clock. Fixes: 969244f9 ("ARM: dts: r7s72100: add ethernet clock to device tree") Signed-off-by:
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- 24 Mar, 2017 1 commit
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Chris Brandt authored
Reported-by:
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- 17 Mar, 2017 1 commit
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Chris Brandt authored
Note that early-bresp-disable and full-line-zero-disable are required because the sideband signals between the CPU and L2C were not connected in this SoC. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk>
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- 10 Mar, 2017 1 commit
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Chris Brandt authored
Add watchdog timer support for RZ/A1. For the RZ/A1, the only way to do a reset is to overflow the WDT, so this is useful even if you don't need the watchdog functionality. Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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- 06 Mar, 2017 1 commit
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Chris Brandt authored
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both need to be enabled/disabled for proper operation. This fixes the fact that the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and that all 4 clock sources need to be defined an used. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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- 25 Jan, 2017 1 commit
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Chris Brandt authored
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- 24 Jan, 2017 2 commits
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Chris Brandt authored
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Chris Brandt authored
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- 04 Nov, 2016 3 commits
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Chris Brandt authored
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Chris Brandt authored
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Chris Brandt authored
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- 17 Oct, 2016 1 commit
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Chris Brandt authored
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- 05 Sep, 2016 2 commits
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Chris Brandt authored
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Chris Brandt authored
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- 27 Mar, 2016 1 commit
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Simon Horman authored
* Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. Signed-off-by:
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- 09 Feb, 2016 2 commits
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Laurent Pinchart authored
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Simon Horman authored
Use GIC_* defines for GIC interrupt cells in r7s72100 device tree. Signed-off-by:
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- 14 Dec, 2015 1 commit
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Geert Uytterhoeven authored
Replace the "arm,cortex-a9-gic" compatible value for the GIC by "arm,pl390", as the documentation states it is a PL390. This has been confirmed (thanks Chris, Wolfram!) by reading the GICD_IIDR register, which reports 0x0000043b (PL390 = 0x00, ARM = 0x43b). This has no effect on runtime behavior, as currently the GIC driver treats both compatible values the same. Signed-off-by:
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- 12 Aug, 2015 1 commit
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Geert Uytterhoeven authored
Add an appropriate "#power-domain-cells" property to the cpg_clocks device node, to create the CPG/MSTP Clock Domain. Add "power-domains" properties to all device nodes for devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock. This applies to most on-SoC devices, which have a one-to-one mapping from SoC device to DT device node. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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- 24 Oct, 2014 1 commit
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Ulrich Hecht authored
Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
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- 09 Sep, 2014 1 commit
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Simon Horman authored
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r7s72100 MTU2 clock source. Signed-off-by:
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- 17 Aug, 2014 1 commit
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Laurent Pinchart authored
Add the MTU2 counter to the r7s72100 device tree and make it disabled by default. Signed-off-by:
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- 17 Jun, 2014 1 commit
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Magnus Damm authored
Add CPU Frequency information to the r7s72100 DTS file. This will allow us to use the shared C code on r7s72100 and Genmai which reads out the clock frequency from DT and calculates the delay settings from there. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Acked-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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- 14 May, 2014 4 commits
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Wolfram Sang authored
Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
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Wolfram Sang authored
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Wolfram Sang authored
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Wolfram Sang authored
Only essential clocks are added for now. Other clocks will be added when needed. Acked-by:
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