- 29 Dec, 2022 19 commits
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8996-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8996 against the yaml documentation. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221223021025.1646636-13-bryan.odonoghue@linaro.org
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8953-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8953 against the yaml documentation. Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8916-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8916 against the yaml documentation. Reviewed-by:
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Krzysztof Kozlowski authored
The bindings expect "mmc" for MMC/SDHCI nodes: sm8350-sony-xperia-sagami-pdx214.dtb: sdhci@8804000: $nodename:0: 'sdhci@8804000' does not match '^mmc(@.*)?$' Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Alex Elder authored
IPA is only needed on a platform if it includes a modem, and not all SC7280 SoC variants do. The file "sc7280-herobrine-lte-sku.dtsi" is used to encapsulate definitions related to Chrome OS SC7280 devices where a modem is present, and that's the proper place for the IPA node to be enabled. Currently IPA is enabled in "sc7280-idp.dtsi", which is included by DTS files for Qualcomm reference platforms (all of which include the modem). That also includes "sc7280-herobrine-lte-sku.dtsi", so enabling IPA there would make it unnecessary for "sc7280-idp.dtsi" to enable it. The only other place IPA is enabled is "sc7280-qcard.dtsi". That file is included only by "sc7280-herobrine.dtsi", which is (eventually) included only by these top-level DTS files: sc7280-herobrine-crd.dts sc7280-herobrine-herobrine-r1.dts sc7280-herobrine-evoker.dts sc7280-herobrine-evoker-lte.dts sc7280-herobrine-villager-r0.dts sc7280-herobrine-villager-r1.dts sc7280-herobrine-villager-r1-lte.dts All of but two of these include "sc7280-herobrine-lte-sku.dtsi", and for those cases, enabling IPA there means there is no need for it to be enabled in "sc7280-qcard.dtsi". The two remaining cases will no longer enable IPA as a result of this change: sc7280-herobrine-evoker.dts sc7280-herobrine-villager-r1.dts Both of these have "lte" counterparts, and are meant to represent board variants that do *not* have a modem. This is exactly the desired configuration. Signed-off-by:
Alex Elder <elder@linaro.org> Reviewed-by:
Sibi Sankar <quic_sibis@quicinc.com> Tested-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Krzysztof Kozlowski authored
This board uses RPMH, specifies "regulator-allow-set-load" for LDOs, but doesn't specify any modes with "regulator-allowed-modes": sm8350-sony-xperia-sagami-pdx214.dtb: regulators-0: ldo5: 'regulator-allowed-modes' is a dependency of 'regulator-allow-set-load' Signed-off-by:
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Konrad Dybcio authored
Add required nodes for MDSS and hook up provided clocks in DISPCC. This setup is almost identical to 8[23]50. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5 Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Years after the SoC support has been added, it's high time for it to get dispcc going. Add the node to ensure that. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5 Reviewed-by:
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Krzysztof Kozlowski authored
Add full cache description to DTS to avoid: 1. "Early cacheinfo failed" warnings, 2. Cache topology detection which leads to early memory allocations and "BUG: sleeping function called from invalid context" on PREEMPT_RT kernel: smp: Bringing up secondary CPUs ... Detected VIPT I-cache on CPU1 BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46 in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1 preempt_count: 1, expected: 0 RCU nest depth: 1, expected: 1 3 locks held by swapper/1/0: #0: ffff5e337eee5f18 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x20c/0xffc #1: ffffa9e24a900b18 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x40/0xe4 #2: ffff5e337efc8918 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x54/0x720 irq event stamp: 0 Call trace: __might_resched+0x17c/0x214 rt_spin_lock+0x5c/0x100 rmqueue_bulk+0x54/0x720 get_page_from_freelist+0xcfc/0xffc __alloc_pages+0xec/0x1150 alloc_page_interleave+0x1c/0xd0 alloc_pages+0xec/0x160 new_slab+0x330/0x454 ___slab_alloc+0x5b8/0xba0 __kmem_cache_alloc_node+0xf4/0x20c __kmalloc+0x60/0x100 detect_cache_attributes+0x2a8/0x5a0 update_siblings_masks+0x28/0x300 store_cpu_topology+0x58/0x70 secondary_start_kernel+0xc8/0x154 Signed-off-by: -
Pierre Gondois authored
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by:Pierre Gondois <pierre.gondois@arm.com> [bjorn: Moved "qcom" to $subject prefix] Signed-off-by:
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Konrad Dybcio authored
With enough pins set properly, the hardware buttons now also work like a charm. Fixes: c2721b0c ("arm64: dts: qcom: Add support for Xperia 1 III / 5 III") Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Xperia 1 III and Xperia 5 III Reviewed-by:
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Gabriela David authored
Add device tree for the Motorola G7 Power (ocean) smartphone. This device is based on Snapdragon 632 (sdm632) SoC which is a variant of MSM8953. Signed-off-by:
Gabriela David <ultracoolguy@disroot.org> Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Eugene Lepshy authored
Add device tree for the Xiaomi Redmi 5 Plus (vince) smartphone. This device is based on Snapdragon 625 (msm8953) SoC. Signed-off-by:
Eugene Lepshy <fekz115@gmail.com> Co-developed-by:
Gianluca Boiano <morf3089@gmail.com> Signed-off-by:
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Danila Tikhonov authored
Add device tree for the Xiaomi Mi A1 (tissot) smartphone. This device is based on Snapdragon 625 (msm8953) SoC. Co-developed-by:
Anton Bambura <jenneron@protonmail.com> Signed-off-by:
Danila Tikhonov <JIaxyga@protonmail.com> Signed-off-by:
Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by:
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Adam Skladowski authored
Add device tree for the Xiaomi Redmi Note 4X (mido) smartphone. This device is based on Snapdragon 625 (msm8953) SoC. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
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Alejandro Tafalla authored
Add device tree for the Xiaomi Mi A2 Lite (daisy) smartphone. This device is based on Snapdragon 625 (msm8953) SoC. Signed-off-by:
Alejandro Tafalla <atafalla@dnyon.com> Signed-off-by:
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Sireesh Kodali authored
Add device tree for the Motorola G5 Plus (potter) smartphone. This device is based on Snapdragon 625 (msm8953) SoC. Signed-off-by:
Sireesh Kodali <sireeshkodali1@gmail.com> Signed-off-by:
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Julian Braha authored
Add device tree for the Motorola Moto G6 (ali) smartphone. This device is based on Snapdragon 450 (sdm450) SoC which is a variant of MSM8953. Signed-off-by:
Julian Braha <julianbraha@gmail.com> Signed-off-by:
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Luca Weiss authored
Adjust node names so they're not just memory@ but actually show what they're used for. Also add labels to most nodes so we can easily reference them from devices. Signed-off-by:
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- 28 Dec, 2022 21 commits
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Dzmitry Sankouski authored
resin node declaration was moved to pm8998.dtsi file (in disabled state). MSM8998 and SDM845 boards defining resin node did not previously have status="okay" and ended up disabled. Re-enable it by using resin node link from pm8998.dtsi with status="okay". Fixes: f86ae6f2 ("arm64: dts: qcom: sagit: add initial device tree for sagit") Signed-off-by:
Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by:
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Youghandhar Chintala authored
Currently, depth-charge Chrome OS bootloader code used in the SC7280 SoC accesses the WiFi node using node names (wifi@<addr>). Since depth-charge Chrome OS bootloader is a common code that is used in SoCs having different WiFi chipsets, it is better if the depth-charge Chrome OS bootloader code accesses the WiFi node using a WiFi alias. The advantage of this method is that the depth-charge Chrome OS bootloader code need not be changed for every new WiFi chip. Therefore, add wifi alias entry for SC7280-idp device tree. Signed-off-by:
Youghandhar Chintala <quic_youghand@quicinc.com> Acked-by:
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Johan Hovold authored
Move the new 'regulator-vph-pwr' node before the wlan regulator node to restore the root-node sort order (alphabetically by node name). While at it, add a couple of newlines to separate the properties for consistency with the other regulator nodes. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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Steev Klimaszewski authored
The firmware paths were pointing to qcom/manufacturer whereas other devices have them under qcom/chipset/manufacturer, so fix this up on the c630, so we follow the same standard setup. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
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Souradeep Chowdhury authored
Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by:
Souradeep Chowdhury <quic_schowdhu@quicinc.com> Signed-off-by:
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Souradeep Chowdhury authored
Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by:
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Souradeep Chowdhury authored
Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by:
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Souradeep Chowdhury authored
Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions. Signed-off-by:
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Marijn Suijten authored
Allow the Adreno GPU to access split pagetables specifically on the dedicated Adreno SMMU via the qcom,adreno-smmu compatible. Signed-off-by:
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Vinod Koul authored
Add the HDMI display nodes and link it to DSI. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Vinod Koul authored
Add the LT9611uxc DSI-HDMI bridge and supplies Signed-off-by:
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Dmitry Baryshkov authored
Enable MDSS/DPU/DSI0 on SM8450-HDK device. Reviewed-by:
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Dmitry Baryshkov authored
Add devices tree nodes describing display hardware on SM8450: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on SM8450. Reviewed-by:
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Dmitry Baryshkov authored
Add another power saving state used on SM8450. Unfortunately adding it in proper place causes renumbering of all the opp states in sm8450.dtsi Reviewed-by:
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Richard Acayan authored
According to the downstream device tree, the regulator that powers the I/O for eMMC should not be turned off. Keep it always on just in case the eMMC driver fails and doesn't enable it, or unloads and disables it. Fixes: 07c8ded6 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Link: https://android.googlesource.com/kernel/msm/+/9ed6ddbe955d3b84d1416a1cf77e83904d1e8421/arch/arm64/boot/dts/google/sdm670-bonito-common.dtsi#105Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Signed-off-by:
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Johan Hovold authored
Move the 'thermal-zones' node after the regulator nodes to restore the root-node sort order (alphabetically by node name). Signed-off-by:
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Konrad Dybcio authored
Remove unnecessary newlines and fix up whitespace near the soundwire controller node. Signed-off-by:
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Konrad Dybcio authored
Use lowercase hex, as that's the preferred and overwhermingly present style. Signed-off-by:
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Konrad Dybcio authored
Use lowercase hex, as that's the preferred and overwhermingly present style. Signed-off-by:
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Konrad Dybcio authored
Use lowercase hex, as that's the preferred and overwhermingly present style. Signed-off-by:
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Konrad Dybcio authored
Use lowercase hex, as that's the preferred and overwhermingly present style. Signed-off-by:
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