- 18 Jan, 2023 40 commits
-
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-17-konrad.dybcio@linaro.org
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Konrad Dybcio authored
One value escaped my previous lowercase hexification. Take care of it. Signed-off-by:
-
Konrad Dybcio authored
Some lines were broken very aggresively, presumably to fit under 80 chars and some places could have used a newline, particularly between subsequent nodes. Address all that and remove redundant comments near PCIe ranges while at it so as not to exceed 100 chars needlessly. Signed-off-by:
-
Konrad Dybcio authored
Order nodes by unit address if one exists and alphabetically otherwise. Signed-off-by:
-
Konrad Dybcio authored
The dwc3 subnode was indented using spaces for some reason and other properties were not exactly properly indented. Fix it. Signed-off-by:
-
Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
-
Abel Vesa authored
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
-
Abel Vesa authored
Add PCIe controllers and PHY nodes. Signed-off-by:
-
Neil Armstrong authored
Add the aDSP, cDSP and MPSS firmware and "Devicetree" firmware paths for the SM8550 MTP platform. Signed-off-by:
-
Neil Armstrong authored
This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by:
-
Abel Vesa authored
Add the interconnect path to SCM dts node. Signed-off-by:
-
Neil Armstrong authored
Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by:
-
Neil Armstrong authored
Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by:
-
Neil Armstrong authored
Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Reviewed-by:
-
Bjorn Andersson authored
Merge the DT binding in order to get the dispcc include file.
-
Neil Armstrong authored
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Pavankumar Kondeti authored
Currently, available frequencies for all CPUs are appearing as 2x of the actual frequencies. Use xo clock source as bi_tcxo in the cpufreq-hw node to fix this. Signed-off-by:
Pavankumar Kondeti <quic_pkondeti@quicinc.com> Tested-by:
-
Markuss Broks authored
The MUIC installed is a part of SM5703 MFD, and it seems to work the same as the SM5502 MUIC unit. Signed-off-by:
Markuss Broks <markuss.broks@gmail.com> [Apply for msm8916-samsung-j5x] Signed-off-by:
Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by:
-
Lin, Meng-Bo authored
Samsung Galaxy J5 2015 and 2016 have a Hall sensor on GPIO pin 52. Add GPIO Hall sensor for them. Signed-off-by:
-
Lin, Meng-Bo authored
After moving msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, Add new J5 2016 device tree. [Add j5x device tree] Co-developed-by:
Josef W Menad <JosefWMenad@protonmail.ch> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
-
Lin, Meng-Bo authored
The smartphones below are using the MSM8916 SoC, which are released in 2015-2016: Samsung Galaxy J5 2015 (SM-J500*) Samsung Galaxy J5 2016 (SM-J510*) Move msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, and add a common device tree for with initial support for: - GPIO keys - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5703 MUIC) - WCNSS (WiFi/BT) - Regulators The two devices (all other variants of J5 released in 2015 and J5X released in 2016) are very similar, with some differences in display and GPIO pins. The common parts are shared in msm8916-samsung-j5-common.dtsi to reduce duplication. This patch rewrites J5 2015 devices, later patches will add support for other models. Signed-off-by:
-
Luca Weiss authored
IPA is used for mobile data. Enable it. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
-
Luca Weiss authored
IPA is used for mobile data. Add a node describing it. Signed-off-by:
-
Konrad Dybcio authored
Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. DDR clock rates come from the vendor kernel. Available values from the HW LUT: 300000000 556800000 652800000 806400000 844800000 940800000 1132800000 1209600000 1286400000 1401600000 1459200000 Signed-off-by:
-
Konrad Dybcio authored
Enable the OSM block responsible for scaling the L3 cache. Signed-off-by:
-
Dmitry Baryshkov authored
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
-
Dmitry Baryshkov authored
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by:
-
Dmitry Baryshkov authored
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by:
-
Dmitry Baryshkov authored
The slope values used during tsens calibration differ between msm8976 and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC. Fixes: 0484d3ce ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Reviewed-by:
-
Alex Elder authored
Depending on the platform, either the modem or the AP must load GSI firmware for IPA before it can be used. To date, this has been indicated by the presence or absence of a "modem-init" property. That mechanism has been deprecated. Instead, we indicate how GSI firmware should be loaded by the value of the "qcom,gsi-loader" property. Update all arm64 platforms that use IPA to use the "qcom,gsi-loader" property to specify how the GSI firmware is loaded. Update the affected nodes so the status property is last. Signed-off-by:
-
