- 27 Jan, 2024 19 commits
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, unify the naming scheme of the thermal zones across the tree while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-11-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-10-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-9-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-8-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-7-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
If the GPU ever reaches this temperature, the "critical" signal shuold definitely be propagated. Fix the wrong type. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-6-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-5-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-4-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-3-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-2-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-1-fda30c57e353@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The RPMh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being committed. Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
Previous Qualcomm SoCs over the past couple years have used the Arm DSU architecture, which basically unified the meaning of the "cluster" and "system". This is however clearly not the case on X1E, as can be seen by three separate cluster power domains. Add the lacking system-level power domain. For now it's going to be always-on, as no system-wide idle states are defined at the moment. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-3-70723e08d5f6@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krishna Kurapati authored
For qcs404 and ipq5332, certain interrupts are missing in DT. Add them to ensure they are in accordance to bindings. The interrupts added enable remote wakeup functionality for these SoCs. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-5-quic_kriskura@quicinc.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krishna Kurapati authored
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Also modify order of interrupts in accordance to bindings update. Modifying the order of these interrupts is harmless as the driver tries to get these interrupts from DT by name and not by index. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-4-quic_kriskura@quicinc.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krishna Kurapati authored
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Also modify order of interrupts in accordance to bindings update. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krishna Kurapati authored
On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq to qusb2_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. Add missing ss_phy_irq on some targets which allows for remote wakeup to work on a Super Speed link. Also modify order of interrupts in accordance to bindings update. Since driver looks up for interrupts by name and not by index, it is safe to modify order of these interrupts in the DT. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Neil Armstrong authored
The SM8550-HDK is an embedded development platforms for the Snapdragon 8 Gen 2 SoC aka SM8550, with the following features: - Qualcomm SM8550 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Product Page: [3] [1] https://www.96boards.org/specifications/ [2] https://git.codelinaro.org/linaro/qcomlt/debugboard [3] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8550-upstream-hdk8550-v3-2-73bb5ef11cf8@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Neil Armstrong authored
Document the Qualcomm SM8550 based HDK (Hardware Development Kit) embedded development platform designed by Qualcomm and sold by Lantronix. [1] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8550-upstream-hdk8550-v3-1-73bb5ef11cf8@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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- 23 Jan, 2024 10 commits
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Konrad Dybcio authored
Add the sleep stats node to enable peeking at the power collapse reports coming from the AOSS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-10-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The AOSS_QMP region is overallocated, bleeding into space that's supposed to be used by other peripherals. Fix it. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-9-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
To guarantee the required resources are enabled, describe the interconnect path between the MDSS and the CPU. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-8-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
To ensure the PLLs are getting enough power, cast a vote with DISPCC so that MMCX is at least at LOW_SVS. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-7-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
There's an OPP table to handle this, drop the permanent vote. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-6-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The (e)DP PHYs are powered by the MX line, not through the MDSS GDSC. Fix that up. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-5-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The CPUs can be powered off without pulling the plug from the rest of the system. Describe the idle state responsible for this. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-4-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The entry latency was oddly low.. Turns out somebody forgot about a second '1'! Fix it. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-3-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
Most of GCC is powered by the CX rail. Describe that relationship to let the performance state requests trickle up the chain. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-2-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The GCC block is (mostly) powered by the VDD_CX rail. Allow specifying it in power-domains. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-1-93b5c107ed43@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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- 22 Jan, 2024 4 commits
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Luca Weiss authored
Enable the venus node so that the video encoder/decoder will start working. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231201-sc7280-venus-pas-v3-3-bc132dc5fc30@fairphone.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Luca Weiss authored
If the video-firmware node is present, the venus driver assumes we're on a system that doesn't use TZ for starting venus, like on ChromeOS devices. Move the video-firmware node to chrome-common.dtsi so we can use venus on a non-ChromeOS devices. We also need to move the secure SID 0x2184 for iommu since (on some boards) we cannot touch that. At the same time also disable the venus node by default in the dtsi, like it's done on other SoCs. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com> Link: https://lore.kernel.org/r/20231201-sc7280-venus-pas-v3-2-bc132dc5fc30@fairphone.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krzysztof Kozlowski authored
Property qcom,drv-count in the RSC node is not allowed and not used: x1e80100-crd.dtb: rsc@17500000: 'qcom,drv-count' does not match any of the regexes: '^regulators(-[0-9])?$', 'pinctrl-[0-9]+' Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231218145050.66394-1-krzysztof.kozlowski@linaro.orgSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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Krishna chaitanya chundru authored
Current MSI's mapping doesn't have all the vectors. This platform supports 8 vectors each vector supports 32 MSI's, so total MSI's supported is 256. Add all the MSI groups supported for this PCIe instance in this platform. Fixes: 92e0ee9f ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") cc: stable@vger.kernel.org Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/20231218-additional_msi-v1-1-de6917392684@quicinc.comSigned-off-by: Bjorn Andersson <andersson@kernel.org>
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- 21 Jan, 2024 7 commits
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Linus Torvalds authored
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https://evilpiepirate.org/git/bcachefsLinus Torvalds authored
Pull more bcachefs updates from Kent Overstreet: "Some fixes, Some refactoring, some minor features: - Assorted prep work for disk space accounting rewrite - BTREE_TRIGGER_ATOMIC: after combining our trigger callbacks, this makes our trigger context more explicit - A few fixes to avoid excessive transaction restarts on multithreaded workloads: fstests (in addition to ktest tests) are now checking slowpath counters, and that's shaking out a few bugs - Assorted tracepoint improvements - Starting to break up bcachefs_format.h and move on disk types so they're with the code they belong to; this will make room to start documenting the on disk format better. - A few minor fixes" * tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs: (46 commits) bcachefs: Improve inode_to_text() bcachefs: logged_ops_format.h bcachefs: reflink_format.h bcachefs; extents_format.h bcachefs: ec_format.h bcachefs: subvolume_format.h bcachefs: snapshot_format.h bcachefs: alloc_background_format.h bcachefs: xattr_format.h bcachefs: dirent_format.h bcachefs: inode_format.h bcachefs; quota_format.h bcachefs: sb-counters_format.h bcachefs: counters.c -> sb-counters.c bcachefs: comment bch_subvolume bcachefs: bch_snapshot::btime bcachefs: add missing __GFP_NOWARN bcachefs: opts->compression can now also be applied in the background bcachefs: Prep work for variable size btree node buffers bcachefs: grab s_umount only if snapshotting ...
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull timer updates from Thomas Gleixner: "Updates for time and clocksources: - A fix for the idle and iowait time accounting vs CPU hotplug. The time is reset on CPU hotplug which makes the accumulated systemwide time jump backwards. - Assorted fixes and improvements for clocksource/event drivers" * tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tick-sched: Fix idle and iowait sleeptime accounting vs CPU hotplug clocksource/drivers/ep93xx: Fix error handling during probe clocksource/drivers/cadence-ttc: Fix some kernel-doc warnings clocksource/drivers/timer-ti-dm: Fix make W=n kerneldoc warnings clocksource/timer-riscv: Add riscv_clock_shutdown callback dt-bindings: timer: Add StarFive JH8100 clint dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
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git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linuxLinus Torvalds authored
Pull powerpc fixes from Aneesh Kumar: - Increase default stack size to 32KB for Book3S Thanks to Michael Ellerman. * tag 'powerpc-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: Increase default stack size to 32KB
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Kent Overstreet authored
Add line breaks - inode_to_text() is now much easier to read. Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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Kent Overstreet authored
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
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