- 04 Apr, 2013 21 commits
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Tomasz Figa authored
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Thomas Abraham <thomas.abraham@linaro.org> Acked-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Tomasz Figa authored
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by:
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Tomasz Figa authored
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by:
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Tomasz Figa authored
This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by:
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Tomasz Figa authored
This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by:
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Tomasz Figa authored
Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by:
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Tomasz Figa authored
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by:
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Tomasz Figa authored
This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by:
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Tomasz Figa authored
This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by:
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Andrzej Hajda authored
The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Tomasz Figa authored
This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by:
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Sylwester Nawrocki authored
This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Tomasz Figa authored
This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by:
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Tomasz Figa authored
Unimplemented clock operations should be simply omitted instead of returning error values. This patch removes unimplemented PLL operations to fix problems caused by returning error code in round_rate callback. Signed-off-by:
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Lukasz Majewski authored
This patch exports clocks used by Exynos cpufreq drivers to allow lookup using device tree. (Support to cpufreq drivers will be added in further patches.) Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com> Signed-off-by:
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Tomasz Figa authored
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12. Signed-off-by:
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Tomasz Figa authored
This clock is used by PCM interface 0. Signed-off-by:
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Tomasz Figa authored
This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by:
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Tomasz Figa authored
This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by:
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Tomasz Figa authored
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by:
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Sylwester Nawrocki authored
This clock must be exported to allow lookup using device tree. Signed-off-by:
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- 28 Mar, 2013 4 commits
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Heiko Stuebner authored
The current code adds aliases, if necessary, directly when adding the clock, limiting the number of possible aliases to one. Some platforms need more than one alias, like the hsmmc pclocks on s3c2416 which need a "hsmmc" and "mmc_busclk.0" alias for the s3c- sdhci driver. Therefore add the possibility to separately add clock aliases for previously created clocks. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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Heiko Stuebner authored
This is needed to allow looking up previous created clocks when adding separate aliases to them. Signed-off-by:
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Heiko Stueber authored
The clock_init function checked for a dt node, returning immediately for non-dt machines. This let to the suspend init never being reached on those non-DT machines. So fix this by moving the pm init code above the check. Signed-off-by:
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Heiko Stuebner authored
On some Samsung platforms divider clocks only use specific divider combinations like the armdiv on s3c2443 and s3c2416. For these usecases the generic divider clock already provides the option of providing a lookup table mapping register values to divider values. Therefore add a new field to samsung_div_clock and if filled with a table, use clk_register_divider_table instead of clk_register_divider to register a divider clock Signed-off-by:
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- 25 Mar, 2013 15 commits
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Thomas Abraham authored
The clock frequency of xxti and xusbxti clocks is dependent on the frequency of the on-board oscillator that is used to generate these clocks. So allow the frequency of these clocks to be specfied from device tree. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos5440, add clock lookup information. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos5250, add clock lookup information. Signed-off-by:
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Thomas Abraham authored
For all supported peripheral controllers on Exynos4 SoCs, add clock lookup information. Reviewed-by:
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Thomas Abraham authored
Add clock controller nodes for EXYNOS4210, EXYNOS4x12, EXYNOS5250 and EXYNOS5440 SoCs. Signed-off-by:
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Thomas Abraham authored
Add support for mct clock lookup and setup to ensure that the mct clock is has been turned on. Signed-off-by:
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Thomas Abraham authored
With the migration of Exynos4 clocks to use common clock framework, the old styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used as the tick clock for mct controller. Signed-off-by:
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Thomas Abraham authored
With support for device tree based clock lookup now available, remove the auxdata table from exynos4/5 dt-enabled machine file. Signed-off-by:
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Thomas Abraham authored
The clock speed of xxti and xusbxti clocks depends on the oscillator used on the board to generate these clocks. For non-dt platforms, allow the board support for those platforms to set the clock frequency of xxti and xusbxti clocks. Signed-off-by:
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Thomas Abraham authored
Since the clock initialization should be completed prior to the mct timer initialization, create a new function 'exynos_init_time' that first sets up the clock and then invokes the timer initialization function. The 'init_time' callback in the board files are updated to invoke this new wrapper function. Signed-off-by:
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Thomas Abraham authored
Remove Samsung specific clock support in Exynos4/5 and migrate to use common clock framework. Reviewed-by:
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Thomas Abraham authored
The Exynos5440 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by:
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Thomas Abraham authored
The Exynos5250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Signed-off-by:
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Thomas Abraham authored
The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by:
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Thomas Abraham authored
There are several types of pll clocks used in Samsung SoC's and these pll clocks can be represented as Samsung specific pll clock types and registered with the common clock framework. Add support for pll35xx, pll36xx, pll45xx, pll46xx and pll2550x clock types and helper functions to register them. Reviewed-by:
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