- 17 May, 2024 2 commits
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Stephen Boyd authored
- STM32MP257 SoC clk driver - Allocate clk_ops dynamically for SCMI clk driver * clk-stm: dt-bindings: clocks: stm32mp25: add access-controllers description clk: stm32: introduce clocks for STM32MP257 platform dt-bindings: clocks: stm32mp25: add description of all parents clk: stm32mp13: use platform device APIs * clk-renesas: clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l: Extend power domain support dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g043-cpg: Add power domain IDs clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT clk: renesas: r8a7740: Remove unused div4_clk.flags field clk: renesas: r9a07g043: Add clock and reset entry for PLIC clk: renesas: r8a779h0: Add INTC-EX clock clk: renesas: r8a779h0: Add MSIOF clocks clk: renesas: r8a779a0: Fix CANFD parent clock clk: rs9: fix wrong default value for clock amplitude clk: renesas: r8a779h0: Add timer clocks clk: renesas: r8a779h0: Add SCIF clocks clk: renesas: r9a07g044: Mark resets array as const clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const clk: renesas: r8a779h0: Add thermal clock dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks * clk-scmi: clk: scmi: Add support for get/set duty_cycle operations clk: scmi: Add support for re-parenting restricted clocks clk: scmi: Add support for rate change restricted clocks clk: scmi: Add support for state control restricted clocks clk: scmi: Allocate CLK operations dynamically * clk-allwinner: clk: sunxi-ng: fix module autoloading clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
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Stephen Boyd authored
Merge branches 'clk-cleanup', 'clk-airoha', 'clk-mediatek', 'clk-sophgo' and 'clk-loongson' into clk-next - Airoha EN7581 SoC clk driver - Sophgo CV1800B, CV1812H and SG2000 SoC clk driver - Loongson-2k0500 and Loongson-2k2000 SoC clk driver * clk-cleanup: clk: gemini: Remove an unused field in struct clk_gemini_pci clk: highbank: Remove an unused field in struct hb_clk clk: ti: dpll: fix incorrect #ifdef checks clk: nxp: Remove an unused field in struct lpc18xx_pll * clk-airoha: clk: en7523: Add EN7581 support clk: en7523: Add en_clk_soc_data data structure dt-bindings: clock: airoha: add EN7581 binding * clk-mediatek: clk: mediatek: mt8365-mm: fix DPI0 parent clk: mediatek: pllfh: Don't log error for missing fhctl node * clk-sophgo: clk: sophgo: avoid open-coded 64-bit division clk: sophgo: Make synthesizer struct static clk: sophgo: Add clock support for SG2000 SoC clk: sophgo: Add clock support for CV1810 SoC clk: sophgo: Add clock support for CV1800 SoC dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC * clk-loongson: clk: clk-loongson2: Add Loongson-2K2000 clock support dt-bindings: clock: loongson2: Add Loongson-2K2000 compatible clk: clk-loongson2: Add Loongson-2K0500 clock support dt-bindings: clock: loongson2: Add Loongson-2K0500 compatible clk: clk-loongson2: Refactor driver for adding new platforms dt-bindings: clock: Add Loongson-2K expand clock index
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- 07 May, 2024 1 commit
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Gabriel Fernandez authored
access-controllers is an optional property that allows to refer to domain access controller. The RCC driver will be able to check if we are allowed to register clocks for a peripheral. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20240419152723.570159-2-gabriel.fernandez@foss.st.comAcked-by:
Rob Herring (Arm) <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 29 Apr, 2024 2 commits
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Miscellaneous fixes and improvements - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car V4M - Add interrupt controller (PLIC) clock and reset on RZ/Five - Prepare power domain support for RZ/G2L family members, and add actual support on RZ/G3S SoC * tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l: Extend power domain support dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g043-cpg: Add power domain IDs clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT clk: renesas: r8a7740: Remove unused div4_clk.flags field clk: renesas: r9a07g043: Add clock and reset entry for PLIC clk: renesas: r8a779h0: Add INTC-EX clock clk: renesas: r8a779h0: Add MSIOF clocks clk: renesas: r8a779a0: Fix CANFD parent clock
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Jernej Skrabec: - Add additional constraints to A64 PLL MIPI clock - Fix autoloading sunxi-ng clocks when build as a module * tag 'sunxi-clk-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: fix module autoloading clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
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- 25 Apr, 2024 9 commits
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Claudiu Beznea authored
Instantiate power domains for the currently enabled IPs of the R9A08G045 SoC. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20240422105355.1622177-8-claudiu.beznea.uj@bp.renesas.comSigned-off-by:
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Claudiu Beznea authored
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra power when clocks are disabled by activating module standby. This is done through MSTOP-specific registers that are part of CPG. Each individual module has one or more bits associated with one MSTOP register (see table "Registers for Module Standby Mode" from HW manuals). Hardware manual associates modules' clocks with one or more MSTOP bits. There are 3 mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) Case 3 has been currently identified on RZ/V2L for the VCPL4 module. To cover all three cases, the individual platform drivers will provide the clock driver with MSTOP register offsets and associated bits in this register as a bitmask, and the clock driver will apply this bitmask to the proper MSTOP register. The MSTOP support was implemented through power domains. Platform-specific clock drivers will register an array of type struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate properly the power domains. Signed-off-by: -
Claudiu Beznea authored
The driver will be modified (in the next commits) to be able to specify individual power domain IDs for each IP. The driver will still support #power-domain-cells = <0>, thus, previous users are not affected. The #power-domain-cells = <1> has been instantiated only for RZ/G3S at the moment, as individual platform clock drivers need to be adapted for this to be supported on the rest of the SoCs. Also, the description for #power-domain-cells is updated with links to per-SoC power domain IDs. Signed-off-by:
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Claudiu Beznea authored
Add power domain IDs for the RZ/G3S (R9A08G045) SoC. Signed-off-by:
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Claudiu Beznea authored
Add power domain IDs for the RZ/V2L (R9A07G054) SoC. Signed-off-by:
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Claudiu Beznea authored
Add power domain IDs for the RZ/G2L (R9A07G044) SoC. Signed-off-by:
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Claudiu Beznea authored
Add power domain IDs for the RZ/G2UL (R9A07G043) SoC. Signed-off-by:
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Geert Uytterhoeven authored
CLK_ENABLE_ON_INIT is a relic from the old SH clock framework. It is not used on SH/R-Mobile ARM drivers. Signed-off-by:
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Christophe JAILLET authored
In "struct div4_clk", the "flags" field is unused. Remove it, and update the "div4_clks" array accordingly. Found with cppcheck, unusedStructMember. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by:
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- 23 Apr, 2024 9 commits
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Lad Prabhakar authored
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list. Fixes: 95d48d27 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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Cong Dang authored
Add the module clock used by the Interrupt Controller for External Devices (INTC-EX) aka IRQC on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
Cong Dang <cong.dang.xn@renesas.com> Signed-off-by:
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Cong Dang authored
Add the module clocks used by the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Geert Uytterhoeven authored
According to Figure 52A.1 ("RS-CANFD Module Block Diagram (in classical CAN mode)") in the R-Car V3U Series User’s Manual Rev. 0.5, the parent clock for the CANFD peripheral module clock is the S3D2 clock. Fixes: 9b621b6a ("clk: renesas: r8a779a0: Add CANFD module clock") Signed-off-by: -
Cristian Marussi authored
Provide the CLK framework callbacks related to get/set clock duty cycle if the related SCMI clock supports OEM extended configurations. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by:
Cristian Marussi <cristian.marussi@arm.com> Link: https://lore.kernel.org/r/20240415163649.895268-6-cristian.marussi@arm.comReviewed-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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Cristian Marussi authored
Some exposed SCMI Clocks could be marked as non-supporting re-parenting changes. Configure a clk_ops descriptor which does not provide the re-parenting callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by:
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Cristian Marussi authored
Some exposed SCMI Clocks could be marked as non-supporting rate changes. Configure a clk_ops descriptors which does not provide the rate change callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by:
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Cristian Marussi authored
Some exposed SCMI Clocks could be marked as non-supporting state changes. Configure a clk_ops descriptor which does not provide the state change callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by:
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Cristian Marussi authored
SCMI Clocks descriptors expose an increasing number of properties, thing which, in turn, leads to a varying set of supported CLK operations to be associated with each clock. Providing statically pre-defined CLK operations structs for all the possible combinations of allowed clock features is becoming cumbersome and error-prone. Allocate the per-clock operations descriptors dynamically and populate it with the strictly needed set of operations depending on the advertised clock properties: one descriptor is created for each distinct combination of clock operations, so minimizing the number of clk_ops structures to the strictly minimum needed. CC: Michael Turquette <mturquette@baylibre.com> CC: Stephen Boyd <sboyd@kernel.org> CC: linux-clk@vger.kernel.org Signed-off-by:
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- 20 Apr, 2024 4 commits
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Catalin Popescu authored
According to 9FGV0241, 9FGV0441 & 9FGV0841 datasheets, the default value for the clock amplitude is 0.8V, while the driver assumes 0.7V. Additionally, define constants for default values for both clock amplitude and spread spectrum and use them. Fixes: 892e0dde ("clk: rs9: Add Renesas 9-series PCIe clock generator driver") Signed-off-by:
Catalin Popescu <catalin.popescu@leica-geosystems.com> Reviewed-by:
Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20240415140348.2887619-1-catalin.popescu@leica-geosystems.comSigned-off-by:
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Christophe JAILLET authored
In "struct clk_gemini_pci", the 'rate' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by:
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Christophe JAILLET authored
In "struct hb_clk", the 'parent_name' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by:
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Alexandre Mergnat authored
To have a working display through DPI, a workaround has been implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to the DPI node. Shortly, that add an extra clock. It seems consistent to have the "dpi0_sel" as parent. Additionnaly, "vpll_dpix" isn't used/managed. Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". The new clock tree is: clk26m lvdspll lvdspll_X (2, 4, 8, 16) dpi0_sel mm_dpi0_dpi0 Fixes: d46adccb ("clk: mediatek: add driver for MT8365 SoC") Signed-off-by:Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20231023-display-support-v3-12-53388f3ed34b@baylibre.comReviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
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- 19 Apr, 2024 2 commits
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Arnd Bergmann authored
On 32-bit architectures, the 64-bit division leads to a link failure: arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate': clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod' This one is not called in a fast path, and there is already another div_u64() variant used in the same function, so convert it to div64_u64_rem(). Fixes: 80fd61ec ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240415134532.3467817-1-arnd@kernel.orgReported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202404140310.QEjZKtTN-lkp@intel.com/Reviewed-by:
Inochi Amaoto <inochiama@outlook.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779h0: Add timer clocks clk: renesas: r8a779h0: Add SCIF clocks clk: renesas: r9a07g044: Mark resets array as const clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const clk: renesas: r8a779h0: Add thermal clock dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
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- 15 Apr, 2024 3 commits
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Krzysztof Kozlowski authored
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Clocks are considered core components, so usually they are built-in, however these can be built and used as modules on some generic kernel. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240410155420.224157-1-krzk@kernel.orgSigned-off-by:
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Frank Oltmanns authored
The Allwinner A64 manual lists the following constraints for the PLL-MIPI clock: - M/N <= 3 - (PLL_VIDEO0)/M >= 24MHz Use these constraints. Reviewed-by:
Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-4-46fc80c83637@oltmanns.devSigned-off-by:
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Frank Oltmanns authored
The Allwinner A64 manual lists the following constraints for the PLL-MIPI clock: - M/N <= 3 - (PLL_VIDEO0)/M >= 24MHz The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for these constraints. Reviewed-by:
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- 12 Apr, 2024 4 commits
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Gabriel Fernandez authored
This driver is intended for the STM32MP25 clock family and utilizes the stm32-core API, similar to the stm32mp13 clock driver. Signed-off-by:
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Gabriel Fernandez authored
RCC driver uses '.index' to define all parent clocks instead '.names' because the use of a name to define a parent clock is discouraged. This is an ABI change, but the RCC driver has not yet merged, unlike all others drivers besides Linux. Fixes: b5be49db ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform") Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240411092453.243633-3-gabriel.fernandez@foss.st.comSigned-off-by:
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Gabriel Fernandez authored
Convert devm_platform_ioremap_resource() and remove unnecessary dependency check with SCMI clock driver. Signed-off-by:
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Inochi Amaoto authored
Let all synthesizer structs are static to make the compiler happy. Fixes: 80fd61ec ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by:
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- 11 Apr, 2024 4 commits
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Binbin Zhou authored
The Loongson-2K2000 and Loongson-2K1000 clock is similar, we add its support by different configurations. Signed-off-by:
Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/8b0b5851783acf8ebe13b50391d15b58cc181613.1712731524.git.zhoubinbin@loongson.cnAcked-by:
Huacai Chen <chenhuacai@loongson.cn> Signed-off-by:
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Binbin Zhou authored
Add the devicetree compatible for Loongson-2K2000 clocks. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/4820325406aec322ae7c062e2b03437d0c95e820.1712731524.git.zhoubinbin@loongson.cnAcked-by:
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Binbin Zhou authored
The Loongson-2K0500 and Loongson-2K1000 clock is similar, we add its support by different configurations. Signed-off-by:
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Binbin Zhou authored
Add the devicetree compatible for Loongson-2K0500 clocks. Signed-off-by:
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