- 29 Aug, 2023 1 commit
-
-
Nathan Chancellor authored
CONFIG_SM_GCC_8450 depends on ARM64 but it is selected by CONFIG_SM_GPUCC_8450, which can be selected on ARM, resulting in a Kconfig warning. WARNING: unmet direct dependencies detected for SM_GCC_8450 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_GPUCC_8450 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Add the same dependencies to CONFIG_SM_GPUCC_8450 to resolve the warning. Fixes: 728692d4 ("clk: qcom: Add support for SM8450 GPUCC") Signed-off-by:
Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20230829-fix-sm_gpucc_8550-deps-v1-1-d751f6cd35b2@kernel.orgReviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
- 22 Aug, 2023 1 commit
-
-
Stephen Boyd authored
Merge tag 'qcom-clk-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Support for the Global Clock Controller in IPQ5018 is added. - The SMD RPM driver is cleaned up, with interconnect bus clocks moved out to the interconnect drivers. Due to being tangled with the related interconnect updates, the topic branch with interconnect patches was merged in as well. - Various bugs in PM runtime integration is fixes across many platforms. - The MSM8996 core bus framework gains support for MSM8996 Pro. - MDM9615 is transitioned to parent_hw and parent_data, with related cleanups. With this the cxo proxy clock is dropped from the driver. And LCC support for MDM9615 is merged into the MSM8960 driver, to avoid duplication. - Network-related resets are added on IPQ4019 - A couple of missing USB-related clocks are added for IPQ9574 - The missing gpll0_sleep_clk_src is added to MSM8917 global clock controller - A few minor fixes for MSM8998 global clock controller. - In the QDU1000 global clock controller GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected. - Missing GDSCs are added to SC8280XP global clock controller driver, flags for existing GDSCs are corrected, by enabling retention and dropping the always-on flags. Retention is also enabled for the display clock controller GDSCs. - SDCC apps_clk_src is marked CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops. - SM6350 GPU clock controller clock supplies are corrected. - Unwanted clocks from the IPQ5332 GCC are dropped. - The missing OXILICX GDSC is added to MSM8226 GCC. - The delay in the reset controller is transitioned to fsleep() to invoke the appropriate sleep method depending on duration. - The SM83550 Video clock controller is extended to support SC8280XP. * tag 'qcom-clk-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (86 commits) clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs ...
-
- 18 Aug, 2023 3 commits
-
-
Konrad Dybcio authored
On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must be always-on as long as the APSS is online and only has to run at 19.2 MHz. Define it to be as such in the ACTIVE domain. Some SoCs use that clock for bus scaling, while others just need it for reaching the hardware. This commit will hurt neither. Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
-
Konrad Dybcio authored
Some clocks, at least PCNoC (a.k.a CNoC_PERIPH) need to be always on, at least on the ACTIVE side, regardless of whether they're used for bus scaling or not. Introduce a new macro to preset non-INT_MAX rates and clk flags to make it easy and work implicitly through the CCF. Signed-off-by:
-
Yang Yingliang authored
lpass_axim_clk_src and lpass_sway_clk_src are only used in gcc-ipq5018.c now, change them to static. Fixes: e3fdbef1 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Reviewed-by:
-
- 15 Aug, 2023 2 commits
-
-
Robert Marko authored
IPQ4019 has more networking related resets that will be required for future wired networking support, so lets add them. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hrSigned-off-by:
-
Robert Marko authored
Add bindings for the missing networking resets found in IPQ4019 GCC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hrSigned-off-by:
-
- 14 Aug, 2023 20 commits
-
-
Otto Pflüger authored
This is the parent clock of gpll0_early, so it needs to be enabled for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC by adding its existing definition to the clock list. This clock also doesn't work with clk_alpha_pll_ops, use clk_branch_simple_ops instead to make it enable and disable correctly. Signed-off-by:
Otto Pflüger <otto.pflueger@abscue.de> Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.deSigned-off-by:
-
Otto Pflüger authored
Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of GPLL0_EARLY. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.deSigned-off-by:
-
Imran Shaik authored
The clock RCGs are required to be parked at safe clock source(XO) during disable as per the hardware expectation and clk_rcg2_shared_ops are the closest implementation for the same. Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by:
-
Imran Shaik authored
Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Signed-off-by:
-
Imran Shaik authored
Add the GDSCs support for QDU1000 and QRU1000 SoCs. Co-developed-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
-
Imran Shaik authored
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware version of QDU1000 and QRU100 SoCs. Signed-off-by:
-
Imran Shaik authored
gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by:
-
Imran Shaik authored
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by:
-
Imran Shaik authored
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by:
-
Imran Shaik authored
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.comSigned-off-by:
-
Konrad Dybcio authored
Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944e ("clk: qcom: Add clock driver for SM8450") Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.orgSigned-off-by:
-
Kathiravan T authored
With the removal of the mem noc clocks in the commit e224dc703521 ("clk: qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the gcc_apss_axi_clk_src clock as well, since there are no clocks uses this clock as a parent. Signed-off-by:Kathiravan T <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.comSigned-off-by:
-
Kathiravan T authored
Due to the recent design changes, all the mem noc clocks will be configured by the bootloaders and it will be access protected by the TZ firmware. So drop these clocks from the GCC driver. Signed-off-by:
-
Konrad Dybcio authored
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by:
-
Konrad Dybcio authored
GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. Add .name lookup to make sure older DTs consume the correct clock. Reviewed-by:
-
Konrad Dybcio authored
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: -
Konrad Dybcio authored
Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by:
-
Konrad Dybcio authored
We've not been consuming that clock for no apparent reason. Describe it. Acked-by:
-
Bjorn Andersson authored
Merge additional MSM8998 GCC DeviceTree binding constants through a topic branch to make them available to the DeviceTree source tree as well.
-
Konrad Dybcio authored
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by:
-
- 11 Aug, 2023 3 commits
-
-
Sricharan Ramabadhran authored
Add support for the global clock controller found on IPQ5018 based devices. Acked-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.comSigned-off-by:
-
Bjorn Andersson authored
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
-
Sricharan Ramabadhran authored
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by:
-
- 04 Aug, 2023 2 commits
-
-
Luca Weiss authored
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae9 ("clk: qcom: Add SM6350 GCC driver") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
-
Konrad Dybcio authored
Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by:
-
- 03 Aug, 2023 3 commits
-
-
Arnd Bergmann authored
The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b10 ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a3 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
-
Patrick Whewell authored
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Patrick Whewell <patrick.whewell@sightlineapplications.com> Reviewed-by:
-
Yang Yingliang authored
The pxo_parent_data inroduced in commit bac4675a ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by:
-
- 31 Jul, 2023 5 commits
-
-
David Wronek authored
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by:
David Wronek <davidwronek@gmail.com> Reviewed-by:
-
Yassine Oudjana authored
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.comSigned-off-by:
-
Yassine Oudjana authored
The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996 and is therefore not fully compatible with it. Add a new compatible string to differentiate between them. Signed-off-by:
-
Dmitry Baryshkov authored
The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
-
Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by:
-
