- 27 Apr, 2022 4 commits
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Chuanhong Guo authored
This driver implements support for the SPI-NAND mode of MTK NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Signed-off-by:
Chuanhong Guo <gch981213@gmail.com> Tested-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Mark Brown authored
Mediatek ECC changes: * Also parse the default nand-ecc-engine property if available * Make mtk_ecc.c a separated module needed for SPI controller driver
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Chuanhong Guo authored
The recently added ECC engine support introduced a generic property named nand-ecc-engine for ecc engine phandle. This patch adds support for this new property. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220424032527.673605-4-gch981213@gmail.com
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Chuanhong Guo authored
this code will be used in mediatek snfi spi-mem controller with pipelined ECC engine. Signed-off-by:
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- 25 Apr, 2022 16 commits
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Mark Brown authored
Merge series from 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>: 1.Add support for using GPIOs as chip select lines on Ingenic SoCs. 2.Add support for probing the spi-ingenic driver on the JZ4775 SoC, the X1000 SoC, and the X2000 SoC. 3.Modify annotation texts to be more in line with the current state.
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Alexander Shiyan authored
Since version 5.13, the standard syscon bindings have been added to all clps711x DT nodes, so we can now use the more general syscon_regmap_lookup_by_phandle function to get the syscon pointer. Signed-off-by:
Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.kernel.org/r/20220420061038.22570-1-eagle.alexander923@gmail.comSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220420090452.2588930-1-chi.minghao@zte.com.cnSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Matthias Schiffer authored
With the removal of the incorrect logic of cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previously allowed 8-8-8 ops). Signed-off-by:
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.comSigned-off-by:
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Matthias Schiffer authored
As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Luca Ceresoli authored
The hardware (except for the ROCKCHIP_SPI_VER2_TYPE2 version) does not support active-high native chip selects. However if such a CS is configured the core does not error as it normally should, because the 'ctlr->use_gpio_descriptors = true' line in rockchip_spi_probe() makes the core set SPI_CS_HIGH in ctlr->mode_bits. In such a case the spi-rockchip driver operates normally but produces an active-low chip select signal without notice. There is no provision in the current core code to handle this situation. Fix by adding a check in the ctlr->setup function (similarly to what spi-atmel.c does). This cannot be done reading the SPI_CS_HIGH but in ctlr->mode_bits because that bit gets always set by the core for master mode (see above). Fixes: eb1262e3 ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods") Signed-off-by:
Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://lore.kernel.org/r/20220421213251.1077899-1-luca.ceresoli@bootlin.comSigned-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by:
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周琰杰 (Zhou Yanjie) authored
1.Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4775-spi" compatible string in the driver. This will permit to support the JZ4775 by having: compatible = "ingenic,jz4775-spi"; Instead of doing: compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi"; 2.Add support for probing the spi-ingenic driver on the X1000 SoC from Ingenic. From the X1000 SoC onwards, the maximum frequency allowed by the SSI module of Ingenic SoCs has been changed from 54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info" to set different maximum frequency values. 3.Add support for probing the spi-ingenic driver on the X2000 SoC from Ingenic. The X2000 SoC has only one native chip select line, so "max_native_cs" is introduced in "jz_soc_info" to set different maximum number of native chip select lines. 4.Because of the introduction of support for the X-series SoCs, the current driver is not only applicable to the JZ-series SoCs, so the description texts has been modified to avoid misunderstanding. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
Add the SPI bindings for the JZ4775 SoC, the X1000 SoC, and the X2000 SoC from Ingenic. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
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周琰杰 (Zhou Yanjie) authored
Add support for using GPIOs as chip select lines on Ingenic SoCs. Signed-off-by:
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- 22 Apr, 2022 1 commit
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Zheng Yongjun authored
If the device is already in a runtime PM enabled state pm_runtime_get_sync() will return 1, so a test for negative value should be used to check for errors. Fixes: deba2580 ("spi: Add driver for IMG SPFI controller") Signed-off-by:
Zheng Yongjun <zhengyongjun3@huawei.com> Link: https://lore.kernel.org/r/20220422062641.10486-1-zhengyongjun3@huawei.comSigned-off-by:
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- 20 Apr, 2022 2 commits
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Mika Westerberg authored
Currently the driver goes over the supported opcodes list each time ->exec_op() is called and finds the suitable for the given operation. This consumes unnecessary amount of CPU cycles because the operation is always the same. For this reason populate dirmap hooks for the driver so that we cache the selected operation and then simply call it on each read/write. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220420104350.19510-1-mika.westerberg@linux.intel.comSigned-off-by:
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Mark Brown authored
Merge series from AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>: This series performs some cleanups to the spi-mt65xx driver, removing all gotos, simplifying the probe function and adding kerneldoc to the driver structures.
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- 19 Apr, 2022 17 commits
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AngeloGioacchino Del Regno authored
Some definitions at the beginning of this file were wrongly indented: fix the indentation for all of these and, while at it, also move the MTK_SPI_IDLE and MTK_SPI_PAUSED down, as to implicitly group the hardware related definitions to the software (driver) related ones. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220407114428.167091-9-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
One of the two structures was already partially documented, but not in kerneldoc format: enhance readability by adding the missing documentation bits and use kerneldoc. Signed-off-by:
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AngeloGioacchino Del Regno authored
Switch to dev_err_probe() to remove all dev_err() -> return repeated patterns, simplifying and shortening the probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
The last goto in the probe function can be removed by calling pm_runtime_enable() right before devm_spi_register_master(), as only some init checks were being performed after enabling pm. This is a cleanup and brings no functional changes. Signed-off-by:
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AngeloGioacchino Del Regno authored
Reparenting sel_clk to parent_clk can be done before enabling any of spi_clk and spi_hclk. Move the call to clk_set_parent() for sel_clk earlier, and call disable_unprepare() upon spi_clk prepare_enable() failure to remove all clock disablement related gotos. This commit is in preparation of a later cleanup. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for switching to dev_err_probe() in this function, add a pointer to struct device and replace all occurrences of '&pdev->dev' to using this 'dev' pointer. This is done for one-line fitting of the dev_err_probe() calls. Signed-off-by:
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AngeloGioacchino Del Regno authored
Instead of performing yet another match check in the probe function, simply switch to device_get_match_data(). This is a cleanup and brings no functional change. Signed-off-by:
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AngeloGioacchino Del Regno authored
Switch to the devm variant of spi_alloc_master() to save some gotos. This patch is a cleanup that brings no functional changes. Signed-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Baruch Siach authored
When SPI_RX_CPHA_FLIP is set, flip CPHA on Rx only transfers. This is useful to access devices that use inverted CPHA for MISO vs MOSI signals. Only support the mx51/mx53 variants for now. Tested on i.MX6ULL based system. Signed-off-by:
Baruch Siach <baruch.siach@siklu.com> Link: https://lore.kernel.org/r/e11b4446afe9a46a282dd923d22c27d03fae15f8.1649702729.git.baruch@tkos.co.ilSigned-off-by:
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Baruch Siach authored
Allow userspace to set SPI_RX_CPHA_FLIP mode bit using the SPI_IOC_WR_MODE32 ioctl. Signed-off-by:
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Baruch Siach authored
Some SPI devices latch MOSI bits on one clock phase, but produce valid MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the controller driver to flip CPHA for Rx (MISO) only transfers. Signed-off-by:
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Mika Westerberg authored
Should be 'specific' not 'spefific'. Fix this. Reported-by:
Hongli Li <hongli.li@intel.com> Signed-off-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Minghao Chi authored
Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by:
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Li-hao Kuo authored
remove spin_lock_irq spin_unlock_irq and variable in the irq funciton Signed-off-by:
Li-hao Kuo <lhjeff911@gmail.com> Link: https://lore.kernel.org/r/f9991d6064d892d22ac7c2dfabe16309e9d03888.1650010304.git.lhjeff911@gmail.comSigned-off-by:
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