- 23 Aug, 2021 1 commit
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Iskren Chernev authored
Add the compatible strings for the UFS PHY found on SM4250/6115 SoC. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210821155657.893165-2-iskren.chernev@gmail.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 20 Aug, 2021 1 commit
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Bjorn Andersson authored
The USB/DP combo PHY exposes the "qmp_dp_phy_pll_link_clk" and "qmp_dp_phy_pll_vco_div_clk" clocks, that are consumed by the display clock controller. But for boards with multiple enabled QMP USB/DP combo instances the hard coded names collides - and hence only the first probed device is allowed to register. Given that clocks are no longer reference globally by name and it's possible to replace the hard coded names by something unique, but still user friendly. The two new clock names are based on dev_name() and results in names such as "88ee000.phy::link_clk" and "88ee000.phy::vco_div_clk". Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210722030738.3385821-1-bjorn.andersson@linaro.orgSigned-off-by:
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- 18 Aug, 2021 1 commit
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Piyush Mehta authored
PHY initialization for USB is required on linux boot or when gt lane is changed from the current one and it is applicable on PLL lock too. Signed-off-by:
Piyush Mehta <piyush.mehta@xilinx.com> Link: https://lore.kernel.org/r/20210818084311.2643986-1-piyush.mehta@xilinx.comSigned-off-by:
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- 17 Aug, 2021 20 commits
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Anand Moon authored
devm_phy_create can return -EPROBE_DEFER if the vbus-supply is not ready yet. Silence this warning as the driver framework will re-attempt registering the PHY. Use dev_err_probe() for phy resources to indicate the deferral reason when waiting for the resource to come up. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20210817041548.1276-7-linux.amoon@gmail.comSigned-off-by:
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Anand Moon authored
Power off the PHY by putting it into reset mode. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Acked-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1629191987-20774-9-git-send-email-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Return the error number directly without assignment Acked-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Acked-by:
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Chunfeng Yun authored
Use clock bulk helpers to get/enable/disable clocks Reviewed-by:
Stanley Chu <stanley.chu@mediatek.com> Signed-off-by:
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Chunfeng Yun authored
devm_ioremap_resource() will print log if error happens. Signed-off-by:
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Chunfeng Yun authored
Print error log using child devices instead of parent device. Signed-off-by:
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Chunfeng Yun authored
Add support type switch between USB3, PCIe, SATA and SGMII by pericfg register, this is used to take the place of efuse or jumper. Signed-off-by:
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Chunfeng Yun authored
Use clock bulk helpers to get/enable/disable clocks Signed-off-by:
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Chunfeng Yun authored
Add support type switch by pericfg register between USB3, PCIe, SATA, SGMII, this is used to replace the way through efuse or jumper. Reviewed-by:
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Swapnil Jakhade authored
PIPE PHY status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.comSigned-off-by:
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Swapnil Jakhade authored
Add debug information in probe regarding PHY configuration parameters like single link or multilink protocol along with number of lanes used for each protocol link. Signed-off-by:
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Swapnil Jakhade authored
Torrent PHY driver currently supports single link DP configuration. Prepare driver to support multilink DP configurations by adding separate functions for common initialization sequence. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.comSigned-off-by:
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Swapnil Jakhade authored
Add PHY configuration registers for single link DP with 100MHz reference clock and NO_SSC. Signed-off-by:
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Swapnil Jakhade authored
Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by:
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Swapnil Jakhade authored
Torrent PHY supports multiple serdes standards with different input reference clock frequencies. PHY register values differ based on the reference clock rate. Add PHY input reference clock frequency as a new dimension to select proper register configuration. No functional change is intended. Signed-off-by:
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Swapnil Jakhade authored
Torrent PHY supports different input reference clock frequencies. Register configurations will be different based on reference clock value. Prepare driver to support such multiple reference clock frequencies. Signed-off-by:
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Swapnil Jakhade authored
Reorder some functions to avoid function declarations. No functional change. Signed-off-by:
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Swapnil Jakhade authored
Script checkpatch with --strict option gives message: CHECK: Avoid CamelCase: <REF_CLK_19_2MHz> CHECK: Avoid CamelCase: <REF_CLK_25MHz> Fix this by removing CamelCase usage. No functional change. Signed-off-by:
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- 06 Aug, 2021 14 commits
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Baruch Siach authored
Initialization is identical to the IPQ8074 USB3 PHY. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/6eec7ef4ecd1e8360ebe8e425151121684e997ed.1628085910.git.baruch@tkos.co.ilSigned-off-by:
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Baruch Siach authored
Add compatible string for USB3 PHY in Qualcomm IPQ6018 SoC. Signed-off-by:
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Biju Das authored
This patch adds USB2.0 PHY support for RZ/G2L SoC. We need to use a different compatible string due to some differences with R-Car Gen3 USB2.0 PHY. It uses line ctrl register for OTG_ID pin changes and different OTG-BC interrupt bit for device recognition. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> # on R-Car Link: https://lore.kernel.org/r/20210727185527.19907-4-biju.das.jz@bp.renesas.comSigned-off-by:
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Biju Das authored
Document USB phy bindings for RZ/G2L SoC. RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses a different OTG-BC interrupt bit for device recognition. Apart from this, the PHY reset is controlled by USBPHY control IP and Document reset is a required property. Signed-off-by:
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Kishon Vijay Abraham I authored
Convert SERDES dt-bindings for TI's AM654 SoC to YAML binding. Signed-off-by:
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Bjorn Andersson authored
The two USB QMPs are USB/DP compbo PHYs, add the compatible for this combination to allow DP output. Signed-off-by:
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Bjorn Andersson authored
The SC8180x has two instances of the QMP USB/DP combo PHYs, add a compatible for these. Signed-off-by:
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Tony Lindgren authored
Since commit 88d26136 ("PM: Prevent runtime suspend during system resume"), PM runtime will not let devices idle during system suspend. This is because of the pm_runtime_get_noresume() call done in device_prepare() that is not released until at device_complete() after resume. We must now disable the USB PHY in suspend if no USB cable is connected. Cc: Andreas Kemnade <andreas@kemnade.info> Signed-off-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210727104512.52968-1-tony@atomide.comSigned-off-by:
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Chunfeng Yun authored
The controller is designed to use use PLL integer mode, but in fact used fractional mode for some ones on mt8195, this causes signal degradation (e.g. eye diagram test fail), fix it by switching PLL to 26Mhz from default 48Mhz to improve signal quality. Signed-off-by:
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Chunfeng Yun authored
The PHYA arch is updated, and doesn't support slew rate calibrate anymore on 7nm or advanced process, add a new version number to support it. Note: the FreqMeter bank is not used but reserved. Signed-off-by:
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Chunfeng Yun authored
The PHYA architecture is updated, and doesn't support slew rate calibration anymore on 7nm or advanced process, add a new version number to support it. Due to the FreqMeter bank is not used but reserved, it's backward with v2 until now. For mt8195, no function changes when use generic v2 or v3 compatible, but prefer to use v3's compatible, it will not waste the time to calibrate the slew rate, and also correspond with hardware version. Acked-by:
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Randy Dunlap authored
Fix errant use of "/**" to begin a comment although the comment is not kernel-doc notation. Just use "/*" instead. Fixes this kernel-doc warning: drivers/phy/qualcomm/phy-qcom-usb-hs.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Copyright (C) 2016 Linaro Ltd Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20210723022548.25695-1-rdunlap@infradead.orgSigned-off-by:
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Dong Aisheng authored
Convert to jason schema. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Li Jun <jun.li@nxp.com> Cc: linux-phy@lists.infradead.org Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by:
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kernel test robot authored
For_each_available_child_of_node should have of_node_put() before break around line 1184. The other jumps out of the loop do contain the put. Generated by: scripts/coccinelle/iterators/for_each_child.cocci CC: Sumera Priyadarsini <sylphrenadin@gmail.com> Reported-by:
Julia Lawall <julia.lawall@inria.fr> Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2106231617540.99238@hadrienSigned-off-by:
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- 22 Jul, 2021 2 commits
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Arnd Bergmann authored
When these are not referenced, gcc prints a harmless warning: drivers/phy/tegra/xusb.c:1286:12: error: 'tegra_xusb_padctl_resume_noirq' defined but not used [-Werror=unused-function] 1286 | static int tegra_xusb_padctl_resume_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/phy/tegra/xusb.c:1276:12: error: 'tegra_xusb_padctl_suspend_noirq' defined but not used [-Werror=unused-function] 1276 | static int tegra_xusb_padctl_suspend_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: c545a905 ("phy: tegra: xusb: Add sleepwalk and suspend/resume") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210721152550.2976003-1-arnd@kernel.orgSigned-off-by:
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Bjorn Andersson authored
A copy paste error was snuck into the patch going upstream that made the SC8180x PCIe PHY use the SM8250 serdes table, but while this works there's some differences in the tables (and the SC8180x was left dangling). So correct the SC8180x definition to use the SC8180x serdes table. Fixes: f839f14e ("phy: qcom-qmp: Add sc8180x PCIe support") Reported-by:
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- 20 Jul, 2021 1 commit
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Chanho Park authored
This patch adds to support phy-exynosautov9-ufs driver for ExynosAuto v9 series SoCs. The patch adds "samsung,exynosautov9-ufs-phy" compatible. Unlike previous exynos ufs phy, the chip uses 0x50 offset as PHY_TRSV_REG_CFG_OFFSET. Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210709094524.110193-3-chanho61.park@samsung.comSigned-off-by:
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