- 29 Sep, 2020 9 commits
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Chiawen Huang authored
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by:
Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Anthony Koo authored
[Header Changes] - Definition for retaining ABM settings during disable - Addition of some new AUX interface definitions - Addition of some outbox definitions Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] At the moment, some tests are failing because cur_link_settings is invalid. As a workaround, add an option to force dio disable. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Joshua Aberback authored
[Why] Currently, when full p-state changes are not supported, DLG parameters are calculated for no p-state support at all. However, we are required to always support dummy p-state changes, so we should instead calculate DLG based on dummy p-state latency when full p-state is unsupported. This behaviour already exists for DCN2. [How] - move DLG calculation inside WM calculation - if p-state unsupported, do not recalculate for set A, instead copy from set C, and perform DLG calculation with dummy p-state latency Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Chiawen Huang authored
[Why] Vbios uses preferred timing to turn on edp but OS could use other timing. If change pixel clock when link active, there is unexpected garbage on monitor. [How] Once pixel clock changed, the driver needs to disable stream. Signed-off-by:
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Wyatt Wood authored
[Why] Some debug bits are not being copied from driver to fw. [How] Copy debug bits properly. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Alvin Lee authored
[Why] HW team measurement requires updating values [How] Update bounding box values Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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- 25 Sep, 2020 16 commits
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Evan Quan authored
Revert the guilty change introduced by the commit below: drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Alex Deucher authored
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(&adev->dev->kobj, &group); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ v2: just print an error for sysfs group creation failure Acked-by:Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Guchun Chen authored
Merge ras sysfs creation together by calling sysfs_create_group once, as sysfs_update_group may not work properly as expected. v2: improve commit message Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Tiecheng Zhou authored
In FLR routine, init_data_exchange is called at reset_sriov while fini_data_exchange is not. This will duplicating work thread. So call fini_data_exchange before reset for SRIOV Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Bokun Zhang authored
- Refactor the driver code to use amdgpu_virt_read_pf2vf_data and amdgpu_virt_write_vf2pf_data instead of writing all code in one function (which is the old amdgpu_virt_init_data_exchange) - Adding a new transaction method for VF2PF message between host and guest driver. Guest side will periodically update VF2PF message in the framebuffer. In the new header, we include guest ucode information, guest framebuffer usage, and engine usage - Clean up the old macros since they will cause compile error if the new transaction method is used v2: squash in build fix Signed-off-by:
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Bokun Zhang authored
- Update guest side VF2PF interface header file Signed-off-by:
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Ryan Taylor authored
Documents PP_FEATURE_MASK enum. Provides instructions on how to use ppfeaturemasks. v2: improve enum definitions and add kernel command line parameters to ppfeaturemask instructions v3: fix alignment issues Signed-off-by:Ryan Taylor <ryan.taylor@amd.com> Reviewed-by:
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John Clements authored
disable UMC RAS in lieu of stability issues on certain sku Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Alex Deucher authored
This allows us to set different defaults on a per asic basis. This way we can enable noretry on dGPUs where it can increase performance in certain cases and disable it on chips where it can be problematic. For now the default is 0 for all asics, but we may want to try and enable it again for newer dGPUs. Reviewed-by:
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Alex Deucher authored
This will allow us to have different defaults per asic in a future patch. Reviewed-by:
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Alex Deucher authored
Properly handle clang and older versions of gcc. Fixes: e77165bf ("drm/amd/display: Add DCN3 blocks to Makefile") Acked-by:
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Emily.Deng authored
Signed-off-by:
Emily.Deng <Emily.Deng@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Jingwen Chen authored
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
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Jingwen Chen authored
smc fw is not needed in SRIOV, thus driver should not try to get smc fw data. Signed-off-by:
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Flora Cui authored
max_caps might be 0, thus hdcp_work might be ZERO_SIZE_PTR Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Jiansong Chen authored
Remove gpu_info fw support for sienna_cichlid etc., since the information can be retrieved from discovery binary. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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- 22 Sep, 2020 15 commits
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Wang Qing authored
Modify the comment typo: "definately" -> "definitely". Signed-off-by:
Wang Qing <wangqing@vivo.com> Signed-off-by:
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Bernard Zhao authored
In the function dal_ddc_service_query_ddc_data, get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. This change is to make the code run a bit fast. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Changes since V1: *get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. Link for V1: *https://lore.kernel.org/patchwork/patch/1309014/Signed-off-by:
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Bernard Zhao authored
Change the comment typo: "programm" -> "program". Signed-off-by:
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Bernard Zhao authored
Change the comment typo: "programm" -> "program". Signed-off-by:
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Ryan Taylor authored
Added IP block section to amdgpu.rst. Added more documentation to amd_ip_funcs. Created documentation for amd_ip_block_type. v2: Provides a more detailed DOC section on IP blocks v3: Clarifies the IP block list. Adds info on IP block enumeration. Signed-off-by:
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Stanley.Yang authored
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Likun Gao authored
Update driver if file for sienna cichlid. Signed-off-by:
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Evan Quan authored
As this is already set inside the implementation of smu_set_watermarks_table(). Signed-off-by:
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Evan Quan authored
As they have no real dependence. And for Navi1x, the socclk/uclk dpms are enabled after DAL initialization. Signed-off-by:
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Evan Quan authored
Otherwise, that will be always true for Navi14. Signed-off-by:
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Stanley.Yang authored
GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next generation, but for some reasons the GCEA/MMHUB EA error will result to DF freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA error as hw fatal error in kernel message by read GCEA/MMHUB err status registers. Changed from V1: make query_ras_error_status function more general make read mmhub er status register more friendly Changed from V2: move ras error status query function into do_recovery workqueue Changed from V3: remove useless code from V2, print GCEA error status instance number Signed-off-by: -
Sudheesh Mavila authored
SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM. Suggested-by:
Sudheesh Mavila <sudheesh.mavila@amd.com> Signed-off-by:
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Evan Quan authored
Different mclk dpm policy will be applied based on the VRAM width. Signed-off-by:
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Liu Shixin authored
Simplify the return expression. Signed-off-by:
Liu Shixin <liushixin2@huawei.com> Signed-off-by:
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Liu Shixin authored
Simplify the return expression. Signed-off-by:
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