- 04 Dec, 2014 3 commits
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Thomas Petazzoni authored
This commit adjusts the registration of the cpufreq-dt driver in the mvebu platform to indicate to the cpufreq driver that the platform has independent clocks for each CPU. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Jason Cooper <jason@lakedaemon.net> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Axel Lin authored
The of_device_id table is supposed to be zero-terminated. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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git://git.infradead.org/linux-mvebuArnd Bergmann authored
Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper: - Armada 370/XP suspend/resume support - mvebu SoC driver suspend/resume support - irqchip - clocksource - mbus - clk * tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller Signed-off-by:
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- 30 Nov, 2014 13 commits
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Thomas Petazzoni authored
The suspend/resume sequence on Armada XP needs to modify a number of registers in the SDRAM controller. Therefore, this commit updates the Armada XP Device Tree description to include the SDRAM controller Device Tree node. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-17-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by:
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Thomas Petazzoni authored
In order to support suspend/resume on Armada XP, an additional set of registers need to be described at the MBus controller level. This commit therefore adjusts the Device Tree of the Armada 370/XP SoC to include those registers in the MBus controller description; Signed-off-by:
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Thomas Petazzoni authored
This commit improves the Armada XP GP Device Tree description to describe the 3 GPIOs that are used to connect the SoC to the PIC micro-controller that we talk to shutdown the SoC when entering suspend to RAM. Signed-off-by:
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Thomas Petazzoni authored
The Armada XP has multiple cores clocked by independent clocks. The SMP startup code contains a function called set_secondary_cpus_clock() called in armada_xp_smp_prepare_cpus() to ensure the clocks of the secondary CPUs match the clock of the boot CPU. With the introduction of suspend/resume, this operation is no longer needed when booting the system, but also when existing the suspend to RAM state. Therefore this commit reworks a bit the logic: instead of configuring the clock of all secondary CPUs in armada_xp_smp_prepare_cpus(), we do it on a per-secondary CPU basis in armada_xp_boot_secondary(), as this function gets called when existing suspend to RAM for each secondary CPU. Since the function now only takes care of one CPU, we rename it from set_secondary_cpus_clock() to set_secondary_cpu_clock(), and it looses its __init marker, as it is now used beyond the system initialization. Note that we can't use smp_processor_id() directly, because when exiting from suspend to RAM, the code is apparently executed with preemption enabled, so smp_processor_id() is not happy (prints a warning). We therefore switch to using get_cpu()/put_cpu(), even though we pretty much have the guarantee that the code starting the secondary CPUs is going to run on the boot CPU and will not be migrated. Signed-off-by:
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Thomas Petazzoni authored
The armada_370_xp_cpu_resume() until now was used only as the function called by the SoC when returning from a deep idle state (as used in cpuidle, or when the CPU is brought offline using CPU hotplug). However, it is now also used when exiting the suspend to RAM state. In this case, it is the bootloader that calls back into this function, with the MMU left enabled by the BootROM. Having the MMU enabled when entering this function confuses the kerrnel because we are not using the kernel page tables at this point, but in other mvebu functions we use the information on whether the MMU is enabled or not to find out whether we should talk to the coherency fabric using a physical address or a virtual address. To fix that, we simply disable the MMU when entering this function, so that the kernel is in an expected situation. Signed-off-by:
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Thomas Petazzoni authored
On the Armada XP GP platform, entering suspend to RAM state is triggering by talking to an external PIC micro-controller connected to the SoC using 3 GPIOs. There is then a small magic sequence of GPIO toggling that needs to be used to tell the PIC to turn off the SoC. The code uses the Device Tree to find out which GPIOs are used to connect to the PIC micro-controller, and then registers its mvebu_armada_xp_gp_pm_enter() callback to the SoC-level PM code. The SoC PM code will call back into this registered function at the very end of the suspend procedure. Signed-off-by:
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Thomas Petazzoni authored
When going out of suspend to RAM, the Marvell EBU platforms go through the bootloader, which re-configures the DRAM controller. To achieve this, the bootloader executes a piece of code called the "DDR3 training code". It does some reads/writes to the memory to find out the optimal timings for the memory chip being used. This has the nasty side effect that the first 10 KB of each DRAM chip-select are overwritten by the bootloader when exiting the suspend to RAM state. Therefore, this commit implements the ->reserve() hook for the 'struct machine_desc' used on Armada XP, to reserve the 10 KB of each DRAM chip-select using the memblock API. Signed-off-by:
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Thomas Petazzoni authored
This commit implements the core of the platform code to enable suspend/resume on Armada XP. It registers the platform_suspend_ops structure, and implements the ->enter() hook of this structure. It is worth mentioning that this commit only provides the SoC-level part of suspend/resume, which calls into some board-specific code provided in a follow-up commit. The most important thing that this SoC-level code has to do is to build an in-memory structure that contains a magic number, the return address in the kernel after resume, and a set of address/value pairs. This structure is used by the bootloader to restore a certain number of registers (according to the set of address/value pairs) and then jump back into the kernel at the provided location. The code also puts the SDRAM into self-refresh mode, before calling into board-specific code to actually enter the suspend to RAM state. [ jac - add email exchange between Andrew Lunn and Thomas Petazzoni to better describe who consumes the address/value pairs ] > > Is this a well defined mechanism supported by mainline uboot, barebox > > etc. Or is it some Marvell extension to their uboot? > > As far as I know, it is a Marvell extension to their "binary header", > so it's done even before U-Boot starts. Since the hardware needs > assistance from the bootloader to do suspend/resume, there is > necessarily a certain amount of cooperation/agreement needed by what > the kernel does and what the bootloader expects. I'm not sure there's > any "standard" mechanism here. Do you know of any? > > I know the suspend/resume on the Blackfin architecture works the same > way (at least it used to work that way years ago when I did a bit of > Blackfin stuff). And here as well, there was some cooperation between > the kernel and the bootloader. See > arch/blackfin/mach-common/dpmc_modes.S, function do_hibernate() at the > end. > Signed-off-by:
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Thomas Petazzoni authored
This commit adds suspend/resume support for the gatable clock driver used on Marvell EBU platforms. When getting out of suspend, the Marvell EBU platforms go through the bootloader, which re-enables all gatable clocks. However, upon resume, the clock framework will not disable again all gatable clocks that are not used. Therefore, if the clock driver does not save/restore the state of the gatable clocks, all gatable clocks that are not claimed by any device driver will remain enabled after a resume. This is why this driver saves and restores the state of those clocks. Since clocks aren't real devices, we don't have the normal ->suspend() and ->resume() of the device model, and have to use the ->suspend() and ->resume() hooks of the syscore_ops mechanism. This mechanism has the unfortunate idea of not providing a way of passing private data, which requires us to change the driver to make the assumption that there is only once instance of the gatable clock control structure. Signed-off-by:
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Thomas Petazzoni authored
On Marvell EBU platforms, when doing suspend/resume, the SDRAM window configuration must be saved on suspend, and restored on resume. However, it needs to be restored on resume *before* re-entering the kernel, because the SDRAM window configuration defines the layout of the memory. For this reason, it cannot simply be done in the ->suspend() and ->resume() hooks of the mvebu-mbus driver. Instead, it needs to be restored by the bootloader "boot info" mechanism used when resuming. This mechanism allows the kernel to define a list of (address, value) pairs when suspending, that the bootloader will restore on resume before jumping back into the kernel. This commit therefore adds a new function to the mvebu-mbus driver, called mvebu_mbus_save_cpu_target(), which will be called by the platform code to make the mvebu-mbus driver save the SDRAM window configuration in a way that can be understood by the bootloader "boot info" mechanism. Signed-off-by:
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Thomas Petazzoni authored
This commit extends the mvebu-mbus driver to provide suspend/resume support. Since mvebu-mbus is not a platform_driver, the syscore_ops mechanism is used to get ->suspend() and ->resume() hooks called into the driver. In those hooks, we save and restore the MBus windows state, to make sure after resume all Mbus windows are properly restored. Note that while the state of some windows could be gathered by looking again at the Device Tree (for statically described windows), it is not the case of dynamically described windows such as the PCIe memory and I/O windows. Therefore, we take the simple approach of saving and restoring the registers for all MBus windows. In addition, the commit extends the Device Tree binding of the MBus controller, to control the MBus bridge registers (which define which parts of the physical address space is routed to MBus windows vs. normal RAM memory). Those registers must be saved and restored during suspend/resume. The Device Tree binding extension is made is a backward compatible fashion, but of course, suspend/resume will not work without the Device Tree update. Signed-off-by:
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Thomas Petazzoni authored
This commit adds a set of suspend/resume syscore_ops to respectively save and restore a number of timer registers, in order to make sure the clockevent and clocksource devices continue to work properly across a suspend/resume cycle. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/1416585613-2113-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by:
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Thomas Petazzoni authored
This commit adds suspend/resume support to the irqchip driver used on Armada XP platforms (amongst others). It does so by adding a set of suspend/resume syscore_ops, that will respectively save and restore the necessary registers to ensure interrupts continue to work after resume. It is worth mentioning that the affinity is lost during a suspend/resume cycle, because when a secondary CPU is brought off-line, all interrupts that are assigned to this CPU in terms of affinity gets re-assigned to a still running CPU. Therefore, right before entering suspend, all interrupts are assigned to the boot CPU. Signed-off-by:
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- 28 Nov, 2014 7 commits
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git://git.infradead.org/linux-mvebuArnd Bergmann authored
Pull "mvebu SoC changes for v3.19" from Jason Cooper: - Armada 38x - Implement CPU hotplug support - Armada 375 - Remove Z1 stepping support (limited dist. of SoC) * tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs ARM: mvebu: Fix the secondary startup for Cortex A9 SoC ARM: mvebu: Move SCU power up in a function ARM: mvebu: Clean-up the Armada XP support ARM: mvebu: update comments in coherency.c ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency ARM: mvebu: remove unused register offset definition ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric ARM: mvebu: Remove thermal quirk for A375 Z1 revision ARM: mvebu: add missing of_node_put() call in coherency.c ARM: orion: Fix for certain sequence of request_irq can cause irq storm ARM: mvebu: armada xp: Generalize use of i2c quirk Signed-off-by: -
Oleksij Rempel authored
Since there is no public documentation, this patch also provide register offsets for different UART units on this SoC. Signed-off-by:
Oleksij Rempel <linux@rempel-privat.de> Signed-off-by:
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Oleksij Rempel authored
it is low cost (?) SoC targeted for market in China and India which trying to compete with AT91SAM9G25. Here is some info: http://www.alphascale.com/index.asp?ics/615.html One of products: http://www.aliexpress.com/store/product/2014-hot-sales-FREE-SHIPPING-new-Purple-core-ARM9-development-board-ASM9260T-SDRAM-power-line/433637_1931495721.html In some cases this SoC looks similar to iMX23/iMX28. But currently it makes no sense to merge mach code of this devices. Especially because most differences are already collected mach-mxs folder. Signed-off-by:
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Arnd Bergmann authored
Merge tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Pull "The i.MX SoC update for 3.19" from Shawn Guo - Update i.MX6 suspend code to check DDR instead of CPU type, as the difference we need to handle is between LPDDR2 and DDR3, not SoCs. - Set anatop properly for LPDDR2 in DSM mode - Add support for new SoC LS1021A which integrates dual Cortex-A7 - Add ENET initialization for i.MX6SX platform - Add cpufreq support for i.MX53 platform - Add a SNVS based poweroff driver for i.MX6 platforms - Use ARM Global Timer as clocksource on VF610 Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve a conflict on file arch/arm/mach-imx/clk-vf610.c. * tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ARM: imx: clk-vf610: get input clocks from assigned clocks ARM: imx: Add Freescale LS1021A SMP support ARM: imx: Add initial support for Freescale LS1021A ARM: imx53: add cpufreq support ARM: imx53: clk: add ARM clock ARM: imx: add CPU clock type ARM: imx5: add step clock, used when reprogramming PLL1 ARM: imx: add enet init for i.mx6sx ARM: imx6sx: add imx6sx iomux-gpr field define ARM: vf610: Add ARM Global Timer clocksource option ARM: imx: add anatop settings for LPDDR2 when enter DSM mode ARM: imx: replace cpu type check with ddr type check ARM: imx: Fix the removal of CONFIG_SPI option ARM: imx: clk-vf610: define PLL's clock tree Signed-off-by; Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge (part of) tag 'omap-for-v3.19/hwmod-and-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps including hwmod clean-up for DSS, and hwmod data for more UARTs and ADC. Also few defconfig changes to enable devices found on am335x and am437x. [arnd: I removed the defconfig changes from the branch in order to cherry-pick them onto the next/defconfig branch, but I did not change the other commits] * commit '29c4ce17': ARM: dts: cm-t3x30: add keypad support ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xx ARM: DRA7: hwmod data: Add missing UART hwmod data ARM: dts: omap4.dtsi: remove dss_fck ARM: OMAP4: fix RFBI iclk ARM: OMAP4: hwmod: use MODULEMODE properly ARM: OMAP4: hwmod: set DSS submodule parent hwmods ARM: OMAP5: hwmod: set DSS submodule parent hwmods ARM: OMAP2+: hwmod: add parent_hwmod support Signed-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim: - exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 * tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf ARM: EXYNOS: move restart code into pmu driver clk: exynos5440: move restart code into clock driver ARM: EXYNOS: add exynos3250 PMU support Signed-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung exynos updates in arch/arm/mach-exynos/ for v3.19" from Kukjin Kim: - add SOC_EXYNOS4415 config to be used in audio driver - add support platform driver for exynos PMU - move PMU specific definitions from common.h to exynos-pmu.h - for exynos5420, add support PMU and Suspend-to-RAM use MCPM call backs and call regulator core suspend prepare and finish functions NOTE: including v3.19-next/non-critical-fixes, v3.19-next/cleanup-samsung and v3.19-next/pm-samsung-2 branches * tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Call regulator core suspend prepare and finish functions ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420 ARM: EXYNOS: Add Suspend-to-RAM support for exynos5420 ARM: EXYNOS: Add PMU support for exynos5420 ARM: EXYNOS: Move PMU specific definitions from common.h ARM: EXYNOS: Add platform driver support for Exynos PMU ARM: EXYNOS: Add support for exynos4415 SoC ARM: EXYNOS: fix typo in static struct name "exynos5_list_diable_wfi_wfe" ARM: EXYNOS: Fix CPU idle clock down after CPU off ARM: EXYNOS: Remove unneeded __ref annotation for cpu_die function ARM: EXYNOS: Move code from hotplug.c to platsmp.c Signed-off-by:
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- 26 Nov, 2014 1 commit
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Bartlomiej Zolnierkiewicz authored
Values stored in val[] are never bigger than a byte. text data bss dec hex filename 7716 3692 8 11416 2c98 arch/arm/mach-exynos/pmu.o.before 5436 1908 8 7352 1cb8 arch/arm/mach-exynos/pmu.o.after Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 23 Nov, 2014 15 commits
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Robin Gong authored
This driver register pm_power_off with snvs power off function. If your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use other pin to do, please disable the driver in dts, otherwise, your pm_power_off maybe overwrote by this driver. Signed-off-by:
Robin Gong <b38343@freescale.com> Acked-By:
Sebastian Reichel <sre@kernel.org> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Arnd Bergmann authored
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which is originally symbol used for the PowerPC based platforms and guards lots of code that does not build on ARM. This breaks allmodconfig, so let's remove it for now, until either all those drivers are fixed or they use a dependency on IMX instead. Signed-off-by:
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Stefan Agner authored
With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Jingchang Lu authored
Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by:
Jingchang Lu <b35083@freescale.com> Signed-off-by:
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Jingchang Lu authored
The LS1021A SoC is a dual-core Cortex-A7 based processor, this adds the initial support for it. Signed-off-by:
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Lucas Stach authored
Instanciate device for the generic cpufreq-dt driver. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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Lucas Stach authored
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Lucas Stach authored
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by:
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Lucas Stach authored
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Fugang Duan authored
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by:
Fugang Duan <B38611@freescale.com> Signed-off-by:
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Fugang Duan authored
Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header file, which is not fully define all iomux-gpr registers and fields, only align with freescale internal tree related GPR macro define. Signed-off-by:
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Stefan Agner authored
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by:
Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by:
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Anson Huang authored
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
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Anson Huang authored
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by:
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Shawn Guo authored
The i.MX fixes for 3.18, 2nd round: - Fix a regression on Vybrid platform which is caused by commit dc4805c2 (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver), and results in a missing configuration on PLL clocks. - Fix a regression with i.MX defconfig files where CONFIG_SPI option gets lost accidentally.
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- 22 Nov, 2014 1 commit
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Pankaj Dubey authored
Let's register restart handler from PMU driver for restart functionality. So that we can remove restart hooks from machine specific file, and thus moving ahead when PMU moved to driver folder, this functionality can be reused for ARM64 based Exynos SoC's. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by:
Guenter Roeck <linux@roeck-us.net> Tested-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
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