- 02 Feb, 2021 5 commits
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Vinod Koul authored
Kryo685 is found in SM8350, so add it to the list of cpu compatibles Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127123054.263231-4-vkoul@kernel.orgSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Vinod Koul authored
Document the SM8350 SoC binding and also the boards using it. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Vincent Knecht authored
Disable MDSS (Mobile Display Subsystem) by default in msm8916.dtsi and only explicitly enable it in devices' DT which actually use it. This leads to faster boot and cleaner logs for other devices, which also won't have to explicitly disable MDSS to use framebuffer. Reviewed-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20210130105717.2628781-4-vincent.knecht@mailoo.orgSigned-off-by:
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Vincent Knecht authored
The Alcatel Idol 3 (4.7") is a smartphone based on MSM8916. Add a device tree with support for USB, eMMC, SD-Card, WiFi, BT, power/volume buttons, vibrator and the following sensors: magnetometer, accelerometer, gyroscope, ambient light+proximity Reviewed-by:
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Vincent Knecht authored
Document vendor prefix for Alcatel Signed-off-by:
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- 26 Jan, 2021 4 commits
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Sai Prakash Ranjan authored
Specify bark interrupt for APSS watchdog to support pre-timeout notification on SM8250 SoC. Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/ff0758b158d62e82fd0636f5861115f435f821ac.1611466260.git.saiprakash.ranjan@codeaurora.orgSigned-off-by:
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Sai Prakash Ranjan authored
Specify bark interrupt for APSS watchdog to support pre-timeout notification on SM8150 SoC. Signed-off-by:
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Sai Prakash Ranjan authored
Specify bark interrupt for APSS watchdog to support pre-timeout notification on SDM845 SoC. Signed-off-by:
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Sai Prakash Ranjan authored
Specify bark interrupt for APSS watchdog to support pre-timeout notification on SC7180 SoC. Signed-off-by:
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- 25 Jan, 2021 12 commits
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Konrad Dybcio authored
I forgot to do this the first time around. Signed-off-by:
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Konrad Dybcio authored
The previous map was wrong. Fix it up. Signed-off-by:
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Konrad Dybcio authored
Fix up the node to make the peripheral functional. Signed-off-by:
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Konrad Dybcio authored
This is required for the GPU to function. Signed-off-by:
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Konrad Dybcio authored
Assign regulators and enable regulator-set-load on VMMC so as to provide sufficient power. Signed-off-by:
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Konrad Dybcio authored
All Kitakami phones use Synaptics RMI4 touchscreens attached to the same i2c bus. Configure and enable it. Signed-off-by:
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Konrad Dybcio authored
Add regulator config for all Kitakami devices, commonizing where applicable. Signed-off-by:
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Konrad Dybcio authored
Rename the fixed regulator to follow the common naming scheme Signed-off-by:
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Konrad Dybcio authored
* Add PMI8994 RPM regulators * Add missing PM8994 LVSes * Add comments concerning "missing" regulators Signed-off-by:
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Konrad Dybcio authored
* Include pm(i)8994 dtsi * Add PMI8994 RPM regulators * Add comments concerning "missing" regulators Signed-off-by:
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Konrad Dybcio authored
This patch adds support for the following Xperias: * Z3+ [aka Z4 in some regions] (Ivy) * Z4 Tablet (Karin) * Z4 Tablet Wi-Fi (Karin_windy) [APQ8094] * Z5 Compact (Suzuran) * Z5 Premium (Satsuki) These devices are very similar in terms of hardware, with main differences being display panels. While at it, update comments describing hardware used: SMB charger seems to not be used after all, PMI8994 charger is in use instead. Signed-off-by:
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Konrad Dybcio authored
Signed-off-by:
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- 22 Jan, 2021 1 commit
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Manivannan Sadhasivam authored
The thermal devicetree binding requires the "-thermal" suffix for all thermal zones. Hence, add the missing suffix for PMIC based thermal zones. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118051005.55958-8-manivannan.sadhasivam@linaro.orgSigned-off-by:
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- 21 Jan, 2021 5 commits
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Eric Biggers authored
Add the registers and clock for the Inline Crypto Engine (ICE) to the device tree node for the sdhci-msm host controller on sdm630. This allows sdhci-msm to support inline encryption on sdm630. Signed-off-by:
Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210121090140.326380-9-ebiggers@kernel.org [bjorn: Changed indentation] Signed-off-by:
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Dmitry Baryshkov authored
Add thermal zones definitions basing on the downstream kernel. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210119054848.592329-6-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Port thermal zones definitions from msm-4.19 tree. Enable and add channel configuration to PMIC's ADC-TM definitions. Declare thermal zones and respective trip points. Signed-off-by:
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Dmitry Baryshkov authored
Define adc-tm5 thermal monitoring part. Individual channes and thermal zones are to be configured in per-device dts files. Signed-off-by:
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AngeloGioacchino Del Regno authored
In commit 208921ba ("arm64: dts: qcom: pmi8998: Add nodes for LAB and IBB regulators") bindings for the lab/ibb regulators were added to the pmi8998 dt, but the original committer has never specified what the interrupts were for. LAB and IBB regulators provide two interrupts, SC-ERR (short circuit error) and VREG-OK but, in that commit, the regulators were provided with two different types of interrupts; specifically, IBB had the SC-ERR interrupt, while LAB had the VREG-OK one, none of which were (luckily) used, since the driver didn't actually use these at all. Assuming that the original intention was to have the SC IRQ in both LAB and IBB, as per the names appearing in documentation, fix the SCP interrupt. While at it, also add the OCP interrupt in order to be able to enable the Over-Current Protection feature, if requested. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by:
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- 19 Jan, 2021 1 commit
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Robert Foss authored
Switch reset pin of ov8856 node from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW, this issue prevented the ov8856 from probing properly as it did not respon to I2C messages. Fixes: d4919a44 ("arm64: dts: qcom: sdm845-db845c: Add ov8856 & ov7251 camera nodes") Signed-off-by:
Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20201221100955.148584-1-robert.foss@linaro.orgSigned-off-by:
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- 16 Jan, 2021 1 commit
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Dmitry Baryshkov authored
Move swr0 device node to keep alphabetical sorting order of device tree nodes. Signed-off-by:
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- 15 Jan, 2021 10 commits
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Dmitry Baryshkov authored
Lower drive strength for microSD data and CMD pins from 16 to 10. This fixes spurious card removal issues observed on some boards. Also this change allows us to re-enable 1.8V support, which seems to work with lowered drive strength. Signed-off-by:
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Matthias Kaehlcke authored
Add labels to the cpuN-thermal nodes to allow board files to use a phandle instead replicating the node hierarchy when adjusting certain properties. Due to the 'sustainable-power' property CPU thermal zones are more likely to need property updates than other SC7180 zones, hence only labels for CPU zones are added for now. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210108141648.1.Ia8019b8b303ca31a06752ed6ceb5c3ac50bd1d48@changeidSigned-off-by:
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Danny Lin authored
Power and performance measurements were made using my freqbench [1] benchmark coordinator, which isolates, offlines, and disables the timer tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as the workload and measures power usage using the PM8150B PMIC's fuel gauge. The energy model dynamic-power-coefficient values were calculated with DPC = µW / MHz / V^2 for each OPP, and averaged across all OPPs within each cluster for the final coefficient. Voltages were obtained from the qcom-cpufreq-hw driver that reads voltages from the OSM LUT programmed into the SoC. Normalized DMIPS/MHz capacity scale values for each CPU were calculated from CoreMarks/MHz (CoreMark iterations per second per MHz), which serves the same purpose. For each CPU, the final capacity-dmips-mhz value is the C/MHz value of its maximum frequency normalized to SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system. A Xiaomi Redmi K30S Ultra device running a downstream Qualcomm 4.19 kernel was used for benchmarking to ensure proper frequency scaling and other low-level controls. Raw benchmark results can be found in the freqbench repository [3]. Below is a human-readable summary: Frequency domains: cpu1 cpu4 cpu7 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Baseline power usage: 1223 mW ===== CPU 1 ===== Frequencies: 300 403 518 614 691 787 883 979 1075 1171 1248 1344 1420 1516 1612 1708 1804 300: 1114 3.7 C/MHz 29 mW 6.4 J 39.0 I/mJ 224.5 s 403: 1497 3.7 C/MHz 33 mW 5.5 J 45.2 I/mJ 167.0 s 518: 1925 3.7 C/MHz 48 mW 6.3 J 39.7 I/mJ 129.9 s 614: 2281 3.7 C/MHz 73 mW 8.0 J 31.1 I/mJ 109.6 s 691: 2566 3.7 C/MHz 46 mW 4.5 J 55.2 I/mJ 97.4 s 787: 2923 3.7 C/MHz 86 mW 7.4 J 33.8 I/mJ 85.5 s 883: 3279 3.7 C/MHz 77 mW 5.9 J 42.5 I/mJ 76.2 s 979: 3635 3.7 C/MHz 65 mW 4.4 J 56.2 I/mJ 68.8 s 1075: 3992 3.7 C/MHz 71 mW 4.4 J 56.2 I/mJ 62.6 s 1171: 4348 3.7 C/MHz 121 mW 6.9 J 36.0 I/mJ 57.5 s 1248: 4633 3.7 C/MHz 79 mW 4.2 J 58.9 I/mJ 54.0 s 1344: 4990 3.7 C/MHz 81 mW 4.0 J 61.7 I/mJ 50.1 s 1420: 5275 3.7 C/MHz 85 mW 4.0 J 61.8 I/mJ 47.4 s 1516: 5632 3.7 C/MHz 88 mW 3.9 J 64.3 I/mJ 44.4 s 1612: 5988 3.7 C/MHz 92 mW 3.8 J 65.4 I/mJ 41.7 s 1708: 6346 3.7 C/MHz 96 mW 3.8 J 66.3 I/mJ 39.4 s 1804: 6701 3.7 C/MHz 105 mW 3.9 J 63.5 I/mJ 37.3 s ===== CPU 4 ===== Frequencies: 710 825 940 1056 1171 1286 1382 1478 1574 1670 1766 1862 1958 2054 2150 2246 2342 2419 710: 6022 8.5 C/MHz 123 mW 5.1 J 49.1 I/mJ 41.5 s 825: 7001 8.5 C/MHz 142 mW 5.1 J 49.4 I/mJ 35.7 s 940: 7987 8.5 C/MHz 164 mW 5.1 J 48.7 I/mJ 31.3 s 1056: 8954 8.5 C/MHz 185 mW 5.2 J 48.3 I/mJ 27.9 s 1171: 9944 8.5 C/MHz 212 mW 5.3 J 46.9 I/mJ 25.2 s 1286: 10926 8.5 C/MHz 235 mW 5.4 J 46.4 I/mJ 22.9 s 1382: 11735 8.5 C/MHz 253 mW 5.4 J 46.4 I/mJ 21.3 s 1478: 12531 8.5 C/MHz 277 mW 5.5 J 45.2 I/mJ 20.0 s 1574: 13335 8.5 C/MHz 306 mW 5.7 J 43.6 I/mJ 18.8 s 1670: 14169 8.5 C/MHz 335 mW 5.9 J 42.2 I/mJ 17.7 s 1766: 14969 8.5 C/MHz 353 mW 5.9 J 42.3 I/mJ 16.7 s 1862: 15800 8.5 C/MHz 444 mW 7.0 J 35.6 I/mJ 15.8 s 1958: 16630 8.5 C/MHz 463 mW 7.0 J 35.9 I/mJ 15.0 s 2054: 17428 8.5 C/MHz 480 mW 6.9 J 36.3 I/mJ 14.4 s 2150: 18238 8.5 C/MHz 496 mW 6.8 J 36.8 I/mJ 13.7 s 2246: 19053 8.5 C/MHz 578 mW 7.6 J 32.9 I/mJ 13.1 s 2342: 19873 8.5 C/MHz 625 mW 7.9 J 31.8 I/mJ 12.6 s 2419: 20522 8.5 C/MHz 675 mW 8.2 J 30.4 I/mJ 12.2 s ===== CPU 7 ===== Frequencies: 844 960 1075 1190 1305 1401 1516 1632 1747 1862 1977 2073 2169 2265 2361 2457 2553 2649 2745 2841 844: 7172 8.5 C/MHz 155 mW 5.4 J 46.4 I/mJ 34.9 s 960: 8148 8.5 C/MHz 172 mW 5.3 J 47.4 I/mJ 30.7 s 1075: 9116 8.5 C/MHz 197 mW 5.4 J 46.2 I/mJ 27.4 s 1190: 10105 8.5 C/MHz 220 mW 5.4 J 46.0 I/mJ 24.8 s 1305: 11084 8.5 C/MHz 242 mW 5.5 J 45.8 I/mJ 22.6 s 1401: 11888 8.5 C/MHz 262 mW 5.5 J 45.4 I/mJ 21.0 s 1516: 12859 8.5 C/MHz 297 mW 5.8 J 43.2 I/mJ 19.5 s 1632: 13840 8.5 C/MHz 335 mW 6.1 J 41.3 I/mJ 18.1 s 1747: 14827 8.5 C/MHz 369 mW 6.2 J 40.1 I/mJ 16.9 s 1862: 15800 8.5 C/MHz 395 mW 6.3 J 40.0 I/mJ 15.8 s 1977: 16786 8.5 C/MHz 443 mW 6.6 J 37.9 I/mJ 14.9 s 2073: 17566 8.5 C/MHz 488 mW 6.9 J 36.0 I/mJ 14.2 s 2169: 18395 8.5 C/MHz 620 mW 8.4 J 29.7 I/mJ 13.6 s 2265: 19223 8.5 C/MHz 621 mW 8.1 J 30.9 I/mJ 13.0 s 2361: 20040 8.5 C/MHz 672 mW 8.4 J 29.8 I/mJ 12.5 s 2457: 20852 8.5 C/MHz 696 mW 8.3 J 29.9 I/mJ 12.0 s 2553: 21684 8.5 C/MHz 738 mW 8.5 J 29.3 I/mJ 11.5 s 2649: 22458 8.5 C/MHz 793 mW 8.8 J 28.3 I/mJ 11.1 s 2745: 23314 8.5 C/MHz 875 mW 9.4 J 26.6 I/mJ 10.7 s 2841: 24103 8.5 C/MHz 928 mW 9.6 J 26.0 I/mJ 10.4 s [1] https://github.com/kdrag0n/freqbench [2] https://www.eembc.org/coremark/ [3] https://github.com/kdrag0n/freqbench/tree/master/results/sm8250/k30sSigned-off-by:Danny Lin <danny@kdrag0n.dev> Link: https://lore.kernel.org/r/20210112013255.415253-2-danny@kdrag0n.devSigned-off-by:
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Danny Lin authored
sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by:
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Stephan Gerhold authored
When the BMC150 accelerometer/magnetometer was added to the device tree, the sensors were working without specifying any regulator supplies, likely because the regulators were on by default and then never turned off. For some reason, this is no longer the case for pm8916_l17, which prevents the sensors from working in some cases. Now that the bmc150_accel/bmc150_magn drivers can enable necessary regulators, declare the necessary regulator supplies to make the sensors work again. Fixes: 079f81ac ("arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometer") Signed-off-by:
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Steev Klimaszewski authored
Running cpufreq-hw driver on Lenovo Yoga C630 laptop, the following warning messages will be seen. [ 3.415340] cpu cpu4: Voltage update failed freq=2841600 [ 3.418755] cpu cpu4: failed to update OPP for freq=2841600 [ 3.422949] cpu cpu4: Voltage update failed freq=2956800 [ 3.427086] cpu cpu4: failed to update OPP for freq=2956800 This is because the cpufreq-hw lookup table of SDM850 provides these two set-points, but they are missing from OPP table in DT. Let's create sdm850.dtsi to add the OPP for them, so that the warning will be gone. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210112090640.20062-1-shawn.guo@linaro.orgSigned-off-by:
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Caleb Connolly authored
Add initial support for the OnePlus 6 (enchilada) and 6T (fajita) based on the sdm845-mtp DT with the following functionality: * Touch * Display * GPU * Wlan and Bluetooth * USB peripheral mode * Remoteproc Reviewed-by:
Caleb Connolly <caleb@connolly.tech> Link: https://lore.kernel.org/r/20210114203057.64541-2-caleb@connolly.techSigned-off-by:
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Dmitry Baryshkov authored
sdhc_2 uses 19200000 Hz clock rather than wrongly specified xo_board (39400000 Hz). Specify correct clock to fix DLL setup for SDR104 mode. Signed-off-by:
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Dmitry Baryshkov authored
Add support for audio output over the HDMI output using Tertiary I2S and LT9611UXC DSI-to-HDMI bridge. Signed-off-by:
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Dmitry Baryshkov authored
Enable Compute DSP (cdsp) on QRB5165-RB5 platform and provide firmware filename used to boot the cdsp. Signed-off-by:
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- 12 Jan, 2021 1 commit
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Danny Lin authored
This commit adds support for deep idling of the entire unified DynamIQ CPU cluster on sm8150. In this idle state, the LLCC (Last-Level Cache Controller) is powered off and the AOP (Always-On Processor) enters a low-power sleep state. I'm not sure what the per-CPU 0x400000f4 idle state previously contributed by Qualcomm as the "cluster sleep" state is, but the downstream kernel has no such state. The real deep cluster idle state is 0x41000c244, composed of: Cluster idle state: (0xc24) << 4 = 0xc240 Is reset state: 1 << 30 = 0x40000000 Affinity level: 1 << 24 = 0x1000000 CPU idle state: 0x4 (power collapse) This setup can be replicated with the PSCI power domain cpuidle driver, which utilizes OSI to enter cluster idle when the last active CPU enters idle. The cluster idle state cannot be used as a plain cpuidle state because it requires that all CPUs in the cluster are idling. Reviewed-by:Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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