- 12 Aug, 2021 1 commit
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Anshuman Gupta authored
dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix state. The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked Wa_14010685332 sequence for every PCH since PCH_CNP. v2: - removed RKL from comment and simplified condition. [Rodrigo] Fixes: b896898c ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms") Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210810113112.31739-2-anshuman.gupta@intel.com
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- 11 Aug, 2021 3 commits
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Matt Roper authored
The SFC_DONE register lives within the corresponding VD0/VD2/VD4/VD6 forcewake domain and is not accessible if the vdbox in that domain is fused off and the forcewake is not initialized. This mistake went unnoticed because until recently we were using the wrong register offset for the SFC_DONE register; once the register offset was corrected, we started hitting errors like <4> [544.989065] i915 0000:cc:00.0: Uninitialized forcewake domain(s) 0x80 accessed at 0x1ce000 on parts with fused-off vdbox engines. Fixes: e50dbdbf ("drm/i915/tgl: Add SFC instdone to error state") Fixes: 82929a21 ("drm/i915: Correct SFC_DONE register offset") Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210806174130.1058960-1-matthew.d.roper@intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Ankit Nautiyal authored
Add the functions to configure HDMI2.1 pcon for DG2, before DP link training. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Ankit Nautiyal authored
Till DISPLAY12 the PIPE_MISC bits 5-7 are used to set the Dithering BPC, with valid values of 6, 8, 10 BPC. For ADLP+ these bits are used to set the PORT OUTPUT BPC, with valid values of: 6, 8, 10, 12 BPC, and need to be programmed whether dithering is enabled or not. This patch: -corrects the bits 5-7 for PIPE MISC register for 12 BPC. -renames the bits and mask to have generic names for these bits for dithering bpc and port output bpc. v3: Added a note for MIPI DSI which uses the PIPE_MISC for readout for pipe_bpp. (Uma Shankar) v2: Added 'display' to the subject and fixes tag. (Uma Shankar) Fixes: 756f85cf ("drm/i915/bdw: Broadwell has PIPEMISC") Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v3.13+ Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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- 06 Aug, 2021 1 commit
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Matt Roper authored
The bspec has been updated with a new revision 0x5 that translates to B1 GT stepping and C0 display stepping. Bspec: 44477 Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-2-matthew.d.roper@intel.com
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- 03 Aug, 2021 2 commits
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José Roberto de Souza authored
Alderlake-P have different values for MBUS DBOX A credits depending if MBUS join is enabled or not. BSpec: 50343 BSpec: 54369 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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Imre Deak authored
CI test results/further experiments show that the workaround added in commit 573d7ce4 ("drm/i915/adlp: Add workaround to disable CMTG clock gating") can be applied only while DPLL0 is enabled. If it's disabled the TRANS_CMTG_CHICKEN register is not accessible. Accordingly move the WA to DPLL0 HW state sanitization and enabling. This fixes an issue where the WA won't get applied (and a WARN is thrown due to an unexpected value in TRANS_CMTG_CHICKEN) if the driver is loaded without DPLL0 being enabled: booting without BIOS enabling an output with this PLL, or reloading the driver. While at it also add a debug print for the unexpected register value. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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- 02 Aug, 2021 2 commits
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Matt Roper authored
The register offset for SFC_DONE was missing a '0' at the end, causing us to read from a non-existent register address. We only use this register in error state dumps so the mistake hasn't caused any real problems, but fixing it will hopefully make the error state dumps a bit more useful for debugging. Fixes: e50dbdbf ("drm/i915/tgl: Add SFC instdone to error state") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Anshuman Gupta authored
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well. Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_MMIO for audio detection and POWER_DOMAIN_AUDIO_PLAYBACK for audio playback. While doing this it requires to use POWER_DOMAIN_AUDIO_MMIO power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask and POWER_DOMAIN_AUDIO_PLAYBACK with intel_display_power_{get, put} to enable/disable display audio codec power. It will save the power in use cases when DP/HDMI connectors configured with PIPE_A without any audio playback. v1: Changes since RFC - changed power domain names. [Imre] - Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1 power well and PW_3 power domains. [Imre] - Fixed the order of powe wells , power domains and its registration. [Imre] v2: - Not allowe DC states when AUDIO_MMIO domain enabled. [Imre] v3: - Squashes the commits of series to avoid build failure. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by:
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- 30 Jul, 2021 25 commits
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Lucas De Marchi authored
With all the users removed, finish removing the CNL platform definitions. We will leave the PCI IDs around as those are exposed to userspace. Even if mesa doesn't support CNL anymore, let's avoid build breakages due to changing the headers. Also, due to drm/i915/gt still using IS_CANNONLAKE() let's just redefine it instead of removing. Signed-off-by:
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Lucas De Marchi authored
Remove registers that are not used anymore due to CNL removal and rename those that are. Signed-off-by:
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Lucas De Marchi authored
Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10. Signed-off-by: -
Lucas De Marchi authored
The numbers of scalers and sprites depend on the display version, so use it instead of GRAPHICS_VER. We were mixing both, which let me confused while removing CNL and GRAPHICS_VER == 10. v2 (Rodrigo): Switch IS_GEMINILAKE to DISPLAY_VER == 10 v3 (Lucas): Change check to DISPLAY_VER >= 9, to cover the GLK's num_scalers, otherwise it remains set to 0. Signed-off-by:
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Lucas De Marchi authored
Cleanup remaining cases that we find CNL in the codebase. Signed-off-by:
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Lucas De Marchi authored
With the removal of CNL, let's consider ICL as the first platform using those constants. Signed-off-by:
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Lucas De Marchi authored
Consider the new WOPCM size as starting in ICL rather than CNL since the latter is being removed from the driver. Signed-off-by:
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Lucas De Marchi authored
Remove references for CNL from pch detection. Signed-off-by:
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Lucas De Marchi authored
Remove support for CNL as it's highly untested, probably broken, and there is no real platform that requires this code. This is part of CNL removal from i915. Signed-off-by:
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Lucas De Marchi authored
Remove special handling of PORT_F in i915_irq.c and only do it for DISPLAY_VER == 11. Signed-off-by:
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Lucas De Marchi authored
With the removal of CNL, let's consider GLK as the first platform using those constants since GLK has DISPLAY_VER == 10. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_display_power.c. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in skl_universal_plane.c. Remove code and rename functions/macros accordingly to use ICL prefix. Signed-off-by:
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Lucas De Marchi authored
Only one reference to CNL that is not needed, but code is the same for DISPLAY_VER >= 11, so leave the code around and just remove the special case for CNL. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_ddi.c. A lot of special code for CNL can be removed. There were some __cnl.*() functions that were created to share the implementation between ICL and CNL. Those are now embedded in the only caller, in ICL. Remove code and rename functions/macros accordingly to use ICL prefix for those that are still needed. Verified with: make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_dp.c. Remove code and rename functions/macros accordingly to use ICL prefix. Signed-off-by:
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Lucas De Marchi authored
Remove DMC firmware for CNL. Signed-off-by:
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Lucas De Marchi authored
Only one reference to CNL that is not needed, but code is the same for DISPLAY_VER >= 11, so leave the code around and just remove the special case for CNL. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to handle CNL explicitly in intel_ddi.c. Remove code and rename functions/macros accordingly to use ICL prefix. There's one leftover reference to cnl that comes from the struct intel_ddi_buf_trans. This will be renamed later when we get rid of the additional CNL tables. Signed-off-by:
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Lucas De Marchi authored
No need for special CNL handling as there is no real platform with that configuration. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have combo phys. We don't need to handle CNL explicitly in intel_combo_phy.c. Remove code and rename functions/macros accordingly to use ICL prefix. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need any checks and supporting code for CNL. For DISPLAY_VER >= 11, ilk_load_csc_matrix() is not used, so make it handle GLK only. Signed-off-by:
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Lucas De Marchi authored
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need any checks and supporting code for CNL. Remove code and rename functions/macros accordingly. Signed-off-by:
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Lucas De Marchi authored
Explicit support for CNL is being removed from the driver as it's not expected to work. Remove the workaround for PORT_F from display/intel_bios.c so we can also remove the generic DISPLAY_VER == 10 calls to intel_ddi_init(): the only platform with that display version is already handled separately (GLK). Signed-off-by:
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- 29 Jul, 2021 6 commits
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Khaled Almahallawy authored
Source needs to write DPCD 103-106 after receiving a PHY request to change swing/pre-emphasis after reading DPCD 206-207. This is especially needed if there is a retimer between source and sink and the retimer implements AUX_CH interception scheme to manage DP PHY settings (e.g. adjusting Swing/Pre-emphasis equalization level) for DP output channel. If the source doesn't write to DPCD 103-106, the retimer may not output the requested swing/pre-emphasis and eventually we fail compliance. v2: Rebase and use crtc->lane_count (Imre) Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Signed-off-by:
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Animesh Manna authored
In verify_mpllb_state() encoder is retrieved from best_encoder of connector_state. As there will be only one connector_state for bigjoiner and checking encoder may not be needed for bigjoiner-slave. This code path related to mpll is done on dg2 and need this fix to avoid null pointer dereference issue. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-30-matthew.d.roper@intel.com
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Gwan-gyeong Mun authored
The PSR enable/disable sequences now require that we program an extra register in the PHY to adjust the lane disable power setting. Bspec: 49274 Bspec: 53885 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Reviewed-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com
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Matt Roper authored
Initialization of the PHY is handled by the hardware/firmware, but the driver should wait up to 25ms for the PHY to report that its calibration has completed. Bspec: 49189 Bspec: 50107 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-28-matthew.d.roper@intel.com
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Matt Roper authored
DG2 has some changes to the expected modesetting sequences when compared to gen12. Adjust our driver logic accordingly. Although the DP sequence is pretty similar to TGL's, there are some steps that change, so let's split the handling for that out into a separate function. v2: - Switch wait_for_us() -> _wait_for() so that we can parameterize the timeout rather than duplicating the macro call. (Jani) Bspec: 54128 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Matt Roper authored
Vswing programming for SNPS PHYs is just a single step -- look up the value that corresponds to the voltage level from a table and program it into the SNPS_PHY_TX_EQ register. Bspec: 53920 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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