- 23 Dec, 2020 4 commits
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Lyude Paul authored
Since we're about to add support for a second type of backlight control interface over DP AUX (specifically, Intel's proprietary HDR backlight controls) let's rename all of the current backlight hooks we have for vesa to make it clear that they're specific to the VESA interface and not Intel's. v3: * Rebase Signed-off-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: thaytan@noraisin.net Cc: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201204223603.249878-6-lyude@redhat.com
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Lyude Paul authored
Instead of using intel_panel->backlight.level, have the caller provide us with the current panel backlight value. We'll need this for when we separate PWM-related backlight callbacks from other means of backlight control (like DPCD backlight controls), as the caller of each PWM callback will be responsible for converting the current brightness value to it's respective PWM level. Signed-off-by:
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Lyude Paul authored
Since we're going to need to add a set of lower-level PWM backlight control hooks to be shared by normal backlight controls and HDR backlight controls in SDR mode, let's add a prefix to the external PWM backlight functions so that the difference between them and the high level PWM-only backlight functions is a bit more obvious. This introduces no functional changes. Signed-off-by:
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Lyude Paul authored
Since we're about to start adding support for Intel's magic HDR backlight interface over DPCD, we need to ensure we're properly programming this field so that Intel specific sink services are exposed. Otherwise, 0x300-0x3ff will just read zeroes. We also take care not to reprogram the source OUI if it already matches what we expect. This is just to be careful so that we don't accidentally take the panel out of any backlight control modes we found it in. v2: * Add careful parameter to intel_edp_init_source_oui() to avoid re-writing the source OUI if it's already been set during driver initialization Signed-off-by:
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- 22 Dec, 2020 5 commits
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Dave Airlie authored
Ville suggested this as a good idea, let's move this before moving the crtc code. Signed-off-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> [Jani: fixed i915xx_plane.h standalone build.] Signed-off-by:
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Dave Airlie authored
This file is a monster, let's start simple, the cursor plane code seems pretty standalone, and splits out easily enough. Reviewed-by:
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Dave Airlie authored
There is no need for a comma use here. Reviewed-by:
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Dave Airlie authored
This will be used for some refactoring in other files, so move it first. Signed-off-by:
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Dave Airlie authored
This function is going to be used in a later change, so clean it up first before moving it. Reviewed-by:
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- 15 Dec, 2020 1 commit
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Ville Syrjälä authored
With GEN11_HOTPLUG_CTL_LONG_DETECT(), SHOTPLUG_CTL_DDI_HPD_LONG_DETECT() and ICP_TC_HPD_LONG_DETECT() taking the hpd_pin as their argument we can remove some duplication in the long_detect() switch statements. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com>
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- 11 Dec, 2020 1 commit
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Sean Paul authored
No need to spam syslog/console when we can ignore/fix the flag. Reviewed-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
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- 10 Dec, 2020 6 commits
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Imre Deak authored
For an enabled DSC during HW readout the corresponding power reference is taken along the CRTC power domain references in get_crtc_power_domains(). Remove the incorrect get ref from the DSI encoder hook. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201209153952.3397959-1-imre.deak@intel.com
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Jani Nikula authored
The VBT fields match the DPCD data, so use the same helper. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Jani Nikula authored
Add a helper for calculating the rc buffer size from the DCPD offsets DP_DSC_RC_BUF_BLK_SIZE and DP_DSC_RC_BUF_SIZE. Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Jani Nikula authored
Move the initialization of the rc_model_size from the common code into encoder code, allowing different encoders to specify the size according to their needs. Keep using the hard coded value in the encoders for now to make this a non-functional change. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
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Jani Nikula authored
The rc_model_size is specified in the DSC config, and the hardware programming should respect that instead of hard coding a value of 8192. Regardless, the rc_model_size in DSC config is currently hard coded to the same value, so this should have no impact, other than allowing the use of other sizes as needed. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
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Jani Nikula authored
The PPS is supposed to reflect the DSC config instead of hard coding the rc_model_size. Make it so. Currently all users of drm_dsc_pps_payload_pack() hard code the size to 8192 also in the DSC config, so this change should have no impact, other than allowing the drivers to use other sizes as needed. Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
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- 08 Dec, 2020 2 commits
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Manasi Navare authored
This patch fixes the slice count computation algorithm for calculating the slice count based on Peak pixel rate and the max slice width allowed on the DSC engines. We need to ensure slice count > min slice count req as per DP spec based on peak pixel rate and that it is greater than min slice count based on the max slice width advertised by DPCD. So use max of these two. In the prev patch we were using min of these 2 causing it to violate the max slice width limitation causing a blank screen on 8K@60. Fixes: d9218c8f ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: <stable@vger.kernel.org> # v5.0+ Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201204205804.25225-1-manasi.d.navare@intel.com
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Manasi Navare authored
The Bspec does not mention polling the FEC Enable Live status bit. That is only there for debug purposes. So remove the polling from driver. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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- 04 Dec, 2020 5 commits
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Chris Wilson authored
Switch off the scanout during driver unregister, so we can shutdown the HW immediately for unbind. v2: Remove the old shutdown from remove, it should now be redundant. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Ville Syrjälä authored
Let's do the kill_bigjoiner_slave() thing from intel_bigjoiner_add_affected_crtcs() since it's related to what we do there. This cleans up the logic in the compute_config() loop a bit. Signed-off-by:
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Ville Syrjälä authored
If either of the bigjoiner pipes needs a modeset then we need a modeset on both pipes. Make it so. v2: Split out the kill_bigjoiner_slave() change (Manasi) Add affected connectors/planes Signed-off-by: -
Ville Syrjälä authored
drm_atomic_add_affected_planes() only considers planes which are logically enabled in the uapi state. For bigjoiner we need to consider planes logically enabled in the hw state. Add a helper for that. Signed-off-by:
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Ville Syrjälä authored
Currently crtc_state->uapi.plane_mask only tracks logically enabled planes on the uapi level. For bigjoiner purposes we want to do the same for the hw state. Let's follow the pattern established by active_planes & co. here. Signed-off-by:
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- 03 Dec, 2020 12 commits
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Manasi Navare authored
VRR_CTL register only had a GENMASK but no field prep define for TRANS_VRR_CTL_LINE_COUNT field so add that Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by:
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Chris Wilson authored
Throw away all the debugfs entries that are not being actively used for debugging/developing IGT. Note that a couple of these are already and will remain available under the gt/ Files removed: i915_gem_fence_regs i915_gem_interrupt i915_ring_freq_table i915_context_status i915_llc i915_shrinker_info Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201202112140.16759-1-chris@chris-wilson.co.uk
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Imre Deak authored
All the display power domain references are wakeref tracked now, so we can mark intel_display_power_put_unchecked() as an internal function (for suppressing wakeref tracking in non-debug builds). Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Add wakeref tracking for the display power domain reference taken to keep the display power well functionality disabled. v2: Add missing wakeref zeroing to intel_power_domains_driver_remove() Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Rename power_domains.wakeref to power_domains.init_wakeref to make the use of this reference clearer. The next patch adds tracking for another power reference user of the power_domains functionality. While at it add a missing zero wakeref assert when setting the wakeref. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Add wakeref tracking for the eDP encoders' AUX display power domain references taken while the panel's VDD is enabled. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Add wakeref tracking for the DDI encoders' main lane AUX display power domain references. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Add wakeref tracking for the DDI encoders' DDI_IO display power domain references. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Add wakeref tracking for display power domain references taken for enabled CRTCs. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Factor out helper functions to get/put a set of power domains that are tracked using their wakeref handles. The same is needed by the next patch adding tracking for enabled CRTC power domains. v2: s/uint64_t/u64/ (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
The for_each_oldnew_intel_crtc_in_state() iterator index does match crtc->pipe, but using the same thing as array index when getting and putting CRTC power domains makes things clearer. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Dave Airlie authored
This moves the functions into static const instead of having funcs and data in the same struct. It leaves the power callback alone, as it is used in a different manner. v2: leave power callback alone (Jani) Reviewed-by:
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- 02 Dec, 2020 4 commits
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Chris Wilson authored
Since we try and estimate how long we require to update the registers to perform a plane update, it is of vital importance that we measure the distribution of plane updates to better guide our estimate. If we underestimate how long it takes to perform the plane update, we may slip into the next scanout frame causing a tear. If we overestimate, we may unnecessarily delay the update to the next frame, causing visible jitter. Replace the warning that we exceed some arbitrary threshold for the vblank update with a histogram for debugfs. v2: Add a per-crtc debugfs entry so that the information is easier to extract when testing individual CRTC, and so that it can be reset before a test. v3: Flip the graph on its side; creates space to label the time axis. Updates: 4684 | 1us | | 4us |******** |********** 16us |*********** |***** 66us | | 262us | | 1ms | | 4ms | | 17ms | | Min update: 5918ns Max update: 54781ns Average update: 16628ns Overruns > 250us: 0 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1982Signed-off-by: -
Jani Nikula authored
Good riddance! Remove the macros and their remaining references in comments. The following functions should be used instead, depending on the use case: - intel_uncore_read(), intel_uncore_write(), intel_uncore_posting_read() - intel_de_read(), intel_de_write(), intel_de_posting_read() Reviewed-by:
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Uma Shankar authored
FBC can be re-enabled on TGL with WA of keeping it disabled while PSR2 is enabled. This reverts commit 2982ded2. Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Uma Shankar authored
There are some corner cases wrt underrun when we enable FBC with PSR2 on TGL. Recommendation from hardware is to keep this combination disabled. Bspec: 50422 HSD: 14010260002 v2: Added psr2 enabled check from crtc_state (Anshuman) Added Bspec link and HSD referneces (Jose) v3: Moved the logic to disable fbc to intel_fbc_update_state_cache and removed the crtc->config usages, as per Ville's recommendation. v4: Introduced a variable in fbc state_cache instead of the earlier plane.visible WA, as suggested by Jose. v5: Dropped an extra check for fbc in intel_fbc_enable and addressed review comments by Jose. v6: Move WA to end of function and added Jose's RB. Signed-off-by:
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