- 30 Mar, 2023 9 commits
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Lad Prabhakar authored
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Biju Das authored
Enable sci0 node using dt overlay and disable can{0,1}-stb-hog nodes in DT overlay as its pins are shared with sci0 pins. Signed-off-by:Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Add support for the 7 PWM channels provided by PWM Timers on R-Car H2, by adding device nodes describing the PWM Timers. Signed-off-by:
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Geert Uytterhoeven authored
Add support for the 4 PWM channels provided by the 16-bit Timer Pulse Unit on R-Car H2, by adding a device node describing the TPU. Signed-off-by:
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Geert Uytterhoeven authored
Enable the single I2C bus available on the Marzen development board. As this bus contains an AK4643 codec, it must be limited to 100 kHz. Signed-off-by:
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Geert Uytterhoeven authored
Describe the four General Purpose Switches on the Marzen development board, so they can be used for user input and/or for wake-up from s2ram. The GPIO block on R-Car H1 does not support triggering interrupts on both edges of a changing input signal, hence one cannot use gpio-keys with gpios properties. Instead, one of two alternatives needs to be used: 1. Use gpio-keys with interrupts instead of gpios properties, at the expense of receiving only key presses (release events will be auto-generated), 2. Use gpio-keys-polled with gpios properties, at the expense of making these keys unusable as wake-up sources. As the DTS for the Marzen development board serves mainly as an example, the approach taken is to use the first alternative for the first two switches, and the second alternative for the last two switches. Signed-off-by: -
Geert Uytterhoeven authored
Add support for the 7 PWM channels provided by PWM Timers on R-Car H1, by describing the PWM Timers and their module clock. Signed-off-by:
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Geert Uytterhoeven authored
Add the module clock used by the PWM Timers on the Renesas R-Car H1 (R8A7779) SoC. Signed-off-by:
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Biju Das authored
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by:
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- 16 Mar, 2023 4 commits
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Geert Uytterhoeven authored
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible property in the CAN-FD device node to include the family-specific compatible value for R-Car Gen4. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the M24C01 I2C EEPROM which serves as external storage for the Ethernet MAC address. While at it, restore sort order (by unit address) of the devices on the I2C bus. Signed-off-by:
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- 10 Mar, 2023 9 commits
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Wolfram Sang authored
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
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Kuninori Morimoto authored
Add R-Car Sound support for the White Hawk board with the ARD-AUDIO-DA7212 external audio board, using a DT overlay. Signed-off-by:
Linh Phung <linh.phung.jy@renesas.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
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Kuninori Morimoto authored
Add sound support for R-Car V4H. Signed-off-by:
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Lad Prabhakar authored
From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 559f2b07 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by:
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Lad Prabhakar authored
From R01UH0936EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: cd0339ec ("arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by:
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Lad Prabhakar authored
From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a34131 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by:
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Geert Uytterhoeven authored
According to the RZ/G Series, 2nd Generation Hardware User’s Manual Rev. 1.11, the System CPU cores on RZ/G2E do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: 231d8908 ("arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices") Signed-off-by:
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Geert Uytterhoeven authored
According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the System CPU cores on R-Car E3 do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: dd7188eb ("arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices") Signed-off-by:
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Lad Prabhakar authored
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/V2L (r9a07g054) SoC. Signed-off-by:
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- 06 Mar, 2023 17 commits
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Niklas Söderlund authored
The sub-board contains two MAX96712 connected to the main-board using I2C and CSI-2, record the connections. Also enable all nodes (VIN, CSI-2 and ISP) that are part of the downstream video capture pipeline. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
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Niklas Söderlund authored
The V4H have 16 VIN, 2 CSI-2 and 2 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by:
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Wolfram Sang authored
The documentation provides information about the placement of the zones, so that can be used for more descriptive labels. Signed-off-by:
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Geert Uytterhoeven authored
Add device nodes for the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) and the various thermal zones on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by:
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Biju Das authored
Add uart0 pins in pinctrl node and update the uart0 node to include pinctrl and uart-has-rtscts properties. Signed-off-by:
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Lad Prabhakar authored
The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by:
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Lad Prabhakar authored
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L (r9a07g044) SoC. Signed-off-by:
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Lad Prabhakar authored
Enable the performance monitor unit for the Cortex-A55 core on the RZ/G2UL (r9a07g043u) SoC. Signed-off-by:
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Geert Uytterhoeven authored
On several R-Car Gen3(e) SoCs, multiple (up to 4) operating points in the same cluster are marked with the "turbo-mode" property, which is meant only for operating points beyond "Normal Mode". Fix this by dropping the property from all operating points but the "High Performance" one. Signed-off-by:
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Nam Nguyen authored
Add the missing clock-skew property for the GEther's Micrel KSZ9031 PHY. Signed-off-by:
Nam Nguyen <nam.nguyen.yh@renesas.com> Signed-off-by:
Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
Describe the 40 MHz Crystal Clock Oscillator providing CAN_CLK. Signed-off-by:
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Fabrizio Castro authored
The RZ/V2M EVK comes with a slot for a uSD card, and an eMMC. Add support for the both of them. Please note that the pinctrl driver for RZ/V2M doesn't support interrupts yet, therefore the card detect pin has been connected to the SDHI IP directly in this patch. We'll connect the card detect pin to its corresponding GPIO when we'll have driver support for interrupts in the RZ/V2M pinctrl driver. Signed-off-by:
Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Enable confirmed-working CAN-FD channels 0 and 1 on the White-Hawk development board: - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be enabled through a GPIO, - Channels 1-7 use Microchip MCP2558FD-H/SN CAN transceivers (not mounted for channels 4-7), which do not need explicit description, but channels 2-3 do not seem to work. Inspired by a patch in the BSP by Kazuya Mizuguch. Signed-off-by: -
Geert Uytterhoeven authored
Add device nodes for the CAN-FD interface and the related external CAN clock on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Kazuya Mizuguch. Signed-off-by:
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Biju Das authored
Enable USB3 role switch on RZ/V2M EVK by linking USB3 peri node with hd3ss3220 controller node. Signed-off-by:
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Biju Das authored
Enable USB3 Host, Peripheral and DRD modules on RZ/V2M EVK. Signed-off-by:
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Biju Das authored
This patch add usb3 host and peripheral device node as child of usb3 drd node to RZ/V2M SoC dtsi. The host/device needs to issue reset release on DRD module before accessing host/device registers. Signed-off-by:
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- 05 Mar, 2023 1 commit
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Linus Torvalds authored
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