- 14 Feb, 2022 1 commit
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Jani Nikula authored
We already have the gem/i915_gem_domain.c file. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Acked-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8208321ad09f1fb0d1a61dc0f2449cce8b23a9b9.1644507885.git.jani.nikula@intel.com
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- 11 Feb, 2022 31 commits
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Ville Syrjälä authored
Remove all the dead code from icl_ddi_bigjoiner_pre_enable(). Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220203183823.22890-6-ville.syrjala@linux.intel.comReviewed-by:
Manasi Navare <manasi.d.navare@intel.com>
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Ville Syrjälä authored
Currently the bigjoiner state copy logic is kind of a byzantine mess. Clean it up to operate in the following manner during a full modeset: 1) master uapi -> hw state copy 2) master hw -> slave hw state copy And during a non-modeset update we do: 1) master uapi -> hw state light copy 2) master hw -> slave hw state light copy I think that is now easier to reason about since we never do any kind of master uapi -> slave hw state copy short circuit that could happen previously. Obviously this does now depend on the master uapi->hw copy always happening before the master hw -> slave hw copy, but that is guaranteed by the fact that we always add both crtcs to the state early, the crtcs are registered in pipe order (so the compute_config loop happens in pipe order), and the hardware requires the master pipe has to be lower than the slave pipe as well. And for good measure we shall add a check+WARN for this before doing the bigjoiner crtc assignment. v2: Fix uapi.ctm vs. hw.ctm copy-paste fail Signed-off-by:
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Ville Syrjälä authored
There's some weird junk in intel_atomic_check_bigjoiner() that's trying to look at the old crtc state's bigjoiner usage for some reason. That code is totally unnecessary, and maybe even actively harmful. Not entirely sure which since it's such a mess that I can't actually wrap my brain around what it ends up doing. Either way, thanks to intel_bigjoiner_add_affected_crtcs() all of the old bigjoiner crtcs are guaranteed to be in the state already if any one of them is in the state. Also if any one of those crtcs got flagged for a modeset, then all of them will have been flagged, and the bigjoiner links will have been detached via kill_bigjoiner_slave(). So there is no need to look examing any old bigjoiner usage in intel_atomic_check_bigjoiner(). All we have to care about is whether bigjoiner is needed for the new state, and whether we can get the slave crtc we need. Signed-off-by:
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Ville Syrjälä authored
We seem to be missing a few things from the bigjoiner state copy. Namely hw.mode isn't getting copied (which probably causes PIPESRC to be misconfigured), CTM/LUTs aren't getting copied (which could cause the pipe to produced incorrect output), and we also forgot to copy over the color_mgmt_changed flag so potentially we fail to do the actual CTM/LUT programming (assuming we aren't doing a full modeset or fastset). Fix it all. v2: Fix uapi.ctm vs. hw.ctm copy-paste fail Signed-off-by:
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Ville Syrjälä authored
The core doesn't flag scaling_filter prop changes as needing a modeset. That doesn't work for us since we only reprogram the pipe scaler during full modesets and fastsets. So we need to flag the prop change as a modeset ourselves. Assuming nothing else has changed the operation will get promoted (demoted?) to a fastset later. Signed-off-by:
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Ville Syrjälä authored
Reuse intel_hdmi_tmds_clock() for DP->HDMI TMDS clock calculations. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com>
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Ville Syrjälä authored
Just loop over the possible bpc values instead of using an ugly if construct. A slight change in behaviour is that we now call intel_hdmi_{source,sink}_bpc_possible() even for 8bpc, but that is fine since 8bpc is always supported. Signed-off-by: -
Ville Syrjälä authored
Extract the dbuf slice data_rate calculation into a small helper. Should make it a bit easier to handle the different color planes of planar formats correctly. Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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Ville Syrjälä authored
Replace some copy-pasta with a function. Signed-off-by:
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Ville Syrjälä authored
Collect a bit of the stuff used during the plane ddb allocation into a struct we can pass around. Signed-off-by:
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Ville Syrjälä authored
We are currently computing the relative data rates as src_size * scale_factor where scale_factor is src_size / dst_size. Thus relative data rate is src_size * src_size / dst_size, which is just utter nonsense. What we really seem to want is just a reasonable estimate on how much data will be fetched which is just src_size. So let's do that instead. Signed-off-by:
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Ville Syrjälä authored
Extract a small helper to populate a ddb entry. Signed-off-by:
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Ville Syrjälä authored
skl_ddb_entry_init_from_hw() has no need for dev_priv. Signed-off-by:
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Jani Nikula authored
We already have the gem/i915_gem_create.c file. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Jani Nikula authored
We already have the gem/i915_gem_dmabuf.c file. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Ville Syrjälä authored
commit c50df701 ("drm/i915: Enable rpm wakeref tracking whether runtime pm is enabled or not") enabled wakeref tracking even for the mock device. Turns out that has somewhat significant overhead, and on the glacial Core m3's we have in CI the vma selftests are now exceeding the allotted time budget. So let's disable the wakeref tracking once again for the mock device in order to avoid blowing up the selftest runtime. Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Acked-by:
Tomi Sarvela <tomi.p.sarvela@intel.com> Signed-off-by:
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Jani Nikula authored
Remove the duplicates. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Jani Nikula authored
We already have the i915_gem_internal.c file. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Jani Nikula authored
128b/132b supports using 64 slots starting from 0, while 8b/10b reserves slot 0 for metadata. Commit d6c6a76f ("drm: Update MST First Link Slot Information Based on Encoding Format") added support for updating the topology state accordingly, and commit 41724ea2 ("drm/amd/display: Add DP 2.0 MST DM Support") started using it in the amd driver. This feels more than a little cumbersome, especially updating the information in atomic check. For i915, add the update to MST connector .compute_config hook rather than iterating over all MST managers and connectors in global mode config .atomic_check. Fingers crossed. v3: - Propagate errors from intel_dp_mst_update_slots() (Ville) v2: - Update in .compute_config() not .atomic_check (Ville) Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Lyude Paul <lyude@redhat.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
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Jani Nikula authored
Abstract link status check to a function that takes 128b/132b and 8b/10b into account, and use it. Also dump link status on failures. Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
The DP 2.0 errata completely overhauls the 128b/132b link training, with no provisions for backward compatibility with the original DP 2.0 specification. The changes are too intrusive to consider reusing the same code for both 8b/10b and 128b/132b, mainly because the LTTPR channel equalisation is done concurrently instead of serialized. NOTES: * It's a bit unclear when to wait for DP_INTERLANE_ALIGN_DONE and per-lane DP_LANE_SYMBOL_LOCKED. Figure xx4 in the SCR implies the LANEx_CHANNEL_EQ_DONE sequence may end with either 0x77,0x77,0x85 *or* 0x33,0x33,0x84 (for four lane configuration in DPCD 0x202..0x204) i.e. without the above bits set. Text elsewhere seems contradictory or incomplete. * We read entire link status (6 bytes) everywhere instead of individual DPCD addresses. * There are some subtle ambiguities or contradictions in the order of some DPCD access and TPS signal enables/disables. It's also not clear whether these are significant. v4: - Wait for intra-hop clear after link training end (Ville) - Wait instead of single check for intra-hop clear before link train v3: - Use msecs_to_jiffies_timeout() (Ville) - Read status at the beginning of interlane align done loop (Ville) - Try to simplify timeout flag use where possible (Ville) v2: - Always try one last time after timeouts to avoid races (Ville) - Extend timeout to cover the entire LANEx_EQ_DONE sequence (Ville) - Also check for eq interlane align done in LANEx_CDS_DONE Sequence (Ville) - Check for Intra-hop status before link training Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Call it from the higher level function, as it will be shared between two code paths. Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Add some of the new additions from DP 2.0 E11. Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/ec9c1b94858de36b9f4ef6c197effa4ca667afc3.1643878928.git.jani.nikula@intel.com
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Jani Nikula authored
The DP 2.0 errata redefines link training. There are some new status bits, and some of the old ones need to be checked independently. Add helpers to do this. Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD 0x2216) completely. Add a new function to read that. Follow-up will need to clean up existing functions. v2: fix reversed interpretation of bit 7 meaning (Uma) Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
We lost the required >>16 when I refactored the FBC plane state checks. Bring it back so the check does what it's supposed to. Cc: Mika Kahola <mika.kahola@intel.com> Fixes: 2e6c99f8 ("drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache") Signed-off-by:
Mika Kahola <mika.kahola@intel.com>
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Jani Nikula authored
Start debug logging about the presence of the new Mailbox #2 for backlight. Actual support is to be added later. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Opregion Mailbox #2 is obsolete for SWSCI usage in opregion v2.x, and repurposed in opregion v3.x. Warn about obsole mailbox presence in v2.x, and ignore with an error for v3.x. v2: Demote drm_warn() to drm_dbg() on opregion v2.x Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Newer platforms aren't supposed to have mailbox #2 or SWSCI support. Bail out early from encoder notify if that is the case, skipping the out-of-bounds checks and debug messages. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Add a reusable function for checking the SWSCI function. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Jani Nikula authored
The mapping from enum port to whatever port numbering scheme is used by the SWSCI Display Power State Notification is odd, and the memory of it has faded. In any case, the parameter only has space for ports numbered [0..4], and UBSAN reports bit shift beyond it when the platform has port F or more. Since the SWSCI functionality is supposed to be obsolete for new platforms (i.e. ones that might have port F or more), just bail out early if the mapped and mangled port number is beyond what the Display Power State Notification can support. Fixes: 9c4b0a68 ("drm/i915: add opregion function to notify bios of encoder enable/disable") Cc: <stable@vger.kernel.org> # v3.13+ Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4800Signed-off-by:
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- 10 Feb, 2022 2 commits
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Jani Nikula authored
The macros are more at home in i915_driver.[ch]. v2: Rebase Reviewed-by:
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Jani Nikula authored
Underscore prefix the index macros, and place INTEL_HWS_CSB_WRITE_INDEX() as a macro next to them, to declutter i915_drv.h. v2: Don't underscore the index macros (Tvrtko) Signed-off-by:
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- 09 Feb, 2022 6 commits
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Ville Syrjälä authored
IPS must be disabled prior to disabling the last plane (excluding the cursor). Make the code do that instead of assuming the primary plane would be the last one. This is probably 100% theoretical as the BIOS should never light up the other planes anyway. But no harm in making the code totally consistent. Also let's update the ips_enabled flag in the crtc state afterwards so that the first atomic commit has accurate information about the state of IPS. Signed-off-by:
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Ville Syrjälä authored
Pull the IPS state readout into hsw_ips.c. Signed-off-by:
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Ville Syrjälä authored
IPS is a pretty well isolated feature. Move the relevant code to a separate file from polluting intel_display.c. I stuck to the hsw_ips name since that's what the function were already using, and also to avoid confusion with the ILK "Intelligen Power Sharing"/intel_ips GPU turbo stuff. And let's also do the s/dev_priv/i915/ rename while touching most of the code. Signed-off-by:
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Ville Syrjälä authored
No reason the caller of the IPS pre/post update hooks should be responsible for the actual IPS enab/disable. Just pull those calls into the pre/post update hooks themselves. And while at it let's adjust the function naming a bit to have a consistent namespace. Signed-off-by:
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Ville Syrjälä authored
Follow the modern state+crtc calling convention for the IPS code as well. Signed-off-by:
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Ville Syrjälä authored
Hoist the IPS related vblank waits one level up. Later on we'll want to consolidate all the potential pre-plane update vblank waits into one so we can't be hiding any in low level code. Signed-off-by:
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