- 04 Oct, 2023 30 commits
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Lijo Lazar authored
Publish max operating temperature of SOC and memory as temp*_emergency nodes in hwmon. temp*_crit will show the throttle temperature limits. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Lijo Lazar authored
CTF limit represents the max operating temperature and thermal limit gives the limit at which throttling starts. Add support for both limits. SOC and HBM may have different limit values.*_emergency_max gives max operating temperature and *_crit_max value represents throttle limit. Signed-off-by:
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Aric Cyr authored
DC v3.2.254 * Stability fixes through null pointer checks, blackscreen fixes on certain configurations * Improvements for various functionality like Idle optimization, ILR, DSC, IPS * Fixes for ILR functionality * Trivial code cleanups =================================================================== Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Make some formatting changes and rearranging of definitions for consistency. Signed-off-by:
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Aurabindo Pillai authored
[Why&How] * Add hints about the bits used in the packed struct. * Update new bitfields for ABM and IPS Signed-off-by:
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Sung Joon Kim authored
[why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. Signed-off-by:
Sung Joon Kim <Sungjoon.Kim@amd.com> Acked-by:
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Wenjing Liu authored
[why] Clip size increase will increase viewport, which could cause us to switch to MPC combine. If we skip full update, we are not able to change to MPC combine in fast update. This will cause corruption showing on the video plane. [how] treat clip size increase of a surface larger than 5k as a full update. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Aric Cyr authored
- Fix constness of string parameters - Fix zero-initialization of structs which cannot take a 0 literal as the first field, for example enums Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Ovidiu Bunea authored
[why] Driver needs to be compatible with PM FW that doesn't support IPS [how] Toggle internal control flag Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
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Sherry Wang authored
[Why] Current ILR toggle is on/off as a part of panel config for new function, which breaks original ILR logic [How] Refactor ILR and take panel config into account Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Sherry Wang <yao.wang1@amd.com> Tested-by:
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Chiawen Huang authored
[Why&How] enable_accelerated_mode function is fully to check whether fastboot support or not. It is no longer to disable_vbios_mode_if_required. Reviewed-by:
Chiawen Huang <chiawen.huang@amd.com> Tested-by:
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Samson Tam authored
[Why] The edge-case DISPCLK WDIVIDER changes call stream_enc functions. But with MPC pipes, downstream pipes have null stream_enc and will cause crash. [How] Only call stream_enc functions for pipes that are OTG master. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Muhammad Ahmed authored
[why] need to enable dsc_clk regardless dsc_pg Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Philip Yang authored
If there is no VRAM domain, bo_node is NULL and this causes crash. Refactor the change, and use the module parameter as higher privilege. Need another patch to support override PTE flag on APU. Fixes: 5f248462 ("drm/amdgpu: Add EXT_COHERENT memory allocation flags") Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
Use ratelimited version of dev_dbg to avoid flooding dmesg log. No functional change. Signed-off-by:
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Gabe Teeger authored
[what and why] Check whether dpp resource pointer is null in advance and return early if so. Reviewed-by:
Martin Leung <martin.leung@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
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Mario Limonciello authored
Several files declare MIN() or MAX() macros that ignore the types of the values being compared. Drop these macros and switch to min() min_t(), and max() from `linux/minmax.h`. Suggested-by:
Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Mario Limonciello authored
The matching values for `pcie_gen_cap` and `pcie_width_cap` when fetched from powerplay tables are 1 byte, so narrow the arguments to match to ensure min() and max() comparisons without casts. Signed-off-by:
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Michel Dänzer authored
If no plane was newly enabled or changed scaling, there can be no new scaling mismatch with the cursor plane. By not pulling non-cursor plane states into all atomic commits while the cursor plane is enabled, this avoids synchronizing all cursor plane changes to vertical blank, which caused the following IGT tests to fail: kms_cursor_legacy@cursor-vs-flip.* kms_cursor_legacy@flip-vs-cursor.* Fixes: 003048dd ("drm/amd/display: Check all enabled planes in dm_check_crtc_cursor") Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Ivan Lipski authored
This reverts commit 44e60b14. Since, it causes a regression in which eDP displays with PSR support, but no Replay support (Sink support <= 0x03), fail to enable PSR and consequently all IGT amd_psr tests fail. So, revert this until a more suitable fix can be found. Cc: stable@vger.kernel.org Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
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Alex Deucher authored
Cache the current fault info in the vm struct. This can be queried by userspace later to help debug UMDs. Cc: samuel.pitoiset@gmail.com Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
When we get a GPU page fault, cache the fault for later analysis. Cc: samuel.pitoiset@gmail.com Reviewed-by:
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Michel Dänzer authored
Cleanup, no functional change intended. Signed-off-by:
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Rajneesh Bhardwaj authored
On GFXIP9.4.3 APU, allow the memory reporting as per the ttm pages limit in NPS1 mode. Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Rajneesh Bhardwaj authored
To allow bigger allocations specially on systems such as GFXIP 9.4.3 that use GTT memory for VRAM allocations, relax the limits to maximize ROCm allocations. Reviewed-by:
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Alex Deucher authored
Needed to avoid a hardware issue. v2: force high for all GC11 parts for consistency (Alex) v3: rebase Reviewed-by:
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Alex Deucher authored
We normally place GART based on the location of VRAM and the available address space around that, but provide an option to force a particular location for hardware that needs it. v2: Switch to passing the placement via parameter Reviewed-by:
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Wayne Lin authored
[Why & How] Fix following problems: - In abm config, forget to initialize config.ambient_thresholds_lux. - Adjust the coding style problem - Restrict to call psr_su_set_dsc_slice_height() under edp only Reviewed-by:
Robin Chen <robin.chen@amd.com> Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Lang Yu authored
Cayn skilfish uses SMUIO v11.0.8 offset. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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- 03 Oct, 2023 10 commits
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Mario Limonciello authored
On some systems with Navi3x dGPU will attempt to use BACO for runtime PM but fails to resume properly. This is because on these systems the root port goes into D3cold which is incompatible with BACO. This happens because in this case dGPU is connected to a bridge between root port which causes BOCO detection logic to fail. Fix the intent of the logic by looking at root port, not the immediate upstream bridge for _PR3. Cc: stable@vger.kernel.org Suggested-by:
Jun Ma <Jun.Ma2@amd.com> Tested-by:
David Perry <David.Perry@amd.com> Fixes: b10c1c5b ("drm/amdgpu: add check for ACPI power resources") Signed-off-by:
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Mario Limonciello authored
While aligning SMU11 with SMU13 implementation an assumption was made that `dpm_context->dpm_tables.pcie_table` was populated in dpm table initialization like in SMU13 but it isn't. So restore some of the original logic and instead just check for amdgpu_device_pcie_dynamic_switching_supported() to decide whether to hardcode values; erring on the side of performance. Cc: stable@vger.kernel.org # 6.1+ Reported-and-tested-by:
Umio Yasuno <coelacanth_dream@protonmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1447#note_2101382 Fixes: e701156c ("drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13") Signed-off-by:
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Alex Hung authored
[WHY] drm_writeback requires to capture exact one frame in each writeback call. [HOW] frame_capture is disabled after each writeback is completed. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Alex Hung authored
[WHAT] Add a function to enable and disable DWB's frame captures. Reviewed-by:
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Alex Hung authored
[WHY] Hardware may require different warmup approaches - big buffer or individual buffers. [HOW] Setup warmup for big buffer when it is required by specific hardware. Reviewed-by:
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Alex Hung authored
[WHAT] Add a new field to keep track whether a crtc is previously writeback-enabled. Reviewed-by:
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Alex Hung authored
[WHY] Counter j was not updated to present the num of writeback_info when writeback pipes are removed. [HOW] update j (num of writeback info) under the correct condition. Reviewed-by:
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Alex Hung authored
[WHAT] hw_points_num is 0 before ogam LUT is programmed; however, function "dwb3_program_ogam_pwl" assumes hw_points_num is always greater than 0, i.e. substracting it by 1 as an array index. [HOW] Check hw_points_num is not equal to 0 before using it. Reviewed-by:
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Alex Hung authored
[WHY] wb_enabled field is set to false before it is used, and the following code will never be executed. [HOW] Setting wb_enable to false after all removal work is completed. Reviewed-by:
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Alex Hung authored
[WHAT] The enable and disable writeback calls need to be included in the coressponding functions in dc_stream. Reviewed-by:
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