- 06 Aug, 2013 5 commits
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Ezequiel Garcia authored
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Ezequiel Garcia authored
Now that mbus has been added to the device tree, it's possible to move the DeviceBus out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Signed-off-by:
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Ezequiel Garcia authored
In order to access the SoC BootROM, we need to declare a mapping (through a ranges property). The mbus driver will use this property to allocate a suitable address decoding window. Signed-off-by:
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Ezequiel Garcia authored
The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by:
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Ezequiel Garcia authored
Signed-off-by:
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- 06 Jun, 2013 1 commit
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Thomas Petazzoni authored
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by:
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- 19 May, 2013 1 commit
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Ezequiel Garcia authored
The Armada XP Development Board (DB-78460-BP) has a NOR flash device connected to the Device Bus. This commit adds the device tree node to support this device. This SoC supports a flexible and dynamic decoding window allocation scheme; but since this feature is still not implemented we need to specify the window base address in the device tree node itself. This base address has been selected in a completely arbitrary fashion. Signed-off-by:
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- 15 May, 2013 1 commit
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Simon Baatz authored
In order to prepare the switch to the standard MMC device tree parser for mvsdio, adapt all current uses of mvsdio in the dts files to the standard format. Signed-off-by:
Simon Baatz <gmbnomis@gmail.com> Signed-off-by:
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- 15 Apr, 2013 4 commits
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Gregory CLEMENT authored
In order to be able to use more than 4GB of RAM when the LPAE is activated, the dts must be converted in 64 bits. Only Armada XP is LPAE capable, but as it shares a common dtsi file with Armada 370, then the common file include the skeleton64. Thanks to the use of the overload capability of the device tree format, armada-370 include the 32 bit skeleton and all the armada 370 based dts can remain the same. This was heavily based on the work of Lior Amsalem. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Gregory CLEMENT authored
Introduce a 'internal-regs' subnode, under which all devices are moved. This is not really needed for now, but will be for the mvebu-mbus driver. This generates a lot of code movement since it's indenting by one more tab all the devices. So it was a good opportunity to fix all the bad indentation. Signed-off-by:
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Gregory CLEMENT authored
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by:
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Thomas Petazzoni authored
The Marvell evaluation board (DB) for the Armada XP SoC has 6 physicals full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by:
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- 28 Feb, 2013 3 commits
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Gregory CLEMENT authored
This patch add support for the SPI flash M25P64 which is present on the Armada XP DB board. This flash stores the bootloader and its environment. Signed-off-by:
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Ezequiel Garcia authored
This patch activates every USB port provided by each SoC. Except for Armada XP Openblocks AX3-4 board, where we enable only the first two USB ports until we have more information on the third one usage. Cc: Lior Amsalem <alior@marvell.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Thomas Petazzoni authored
The Armada XP DB evaluation board has one SD card slot, directly connected to the SDIO IP of the SoC, so we enable this IP. Unfortunately, there are no GPIOs for card-detect and write-protect. Signed-off-by:
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- 20 Nov, 2012 2 commits
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Thomas Petazzoni authored
The mvneta driver for the Marvell Armada 370/XP Ethernet devices has gained proper clock framework integration, and the corresponding Device Tree nodes now have a correct 'clocks' pointer. The 'clock-frequency' properties in the various .dts files for Armada 370/XP boards have therefore become useless. Signed-off-by: -
Gregory CLEMENT authored
Add the SATA device tree bindings for - Armada XP evaluation board (DB-78460-BP) - Armada 370 evaluation board (DB-88F6710-BP-DDR3) Signed-off-by:
Lior Amsalem <alior@marvell.com> Signed-off-by:
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- 16 Nov, 2012 1 commit
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Thomas Petazzoni authored
This patch enables the two network interfaces of the Armada 370 official Marvell evaluation platform, and the four network interfaces of the Armada XP official Marvell evaluation platform. Signed-off-by:
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- 22 Sep, 2012 1 commit
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Thomas Petazzoni authored
The Armada XP evaluation board is based on the MV78460 Armava XP SoC. Now that we have separate .dtsi files for the three different SoCs of the Armada XP family, use the appropriate one as include for the Armada XP evaluation board .dts file. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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- 10 Jul, 2012 1 commit
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Thomas Petazzoni authored
[ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32] [ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ] [ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic] [ben.dooks@codethink.co.uk: move mpic per-cpu register base ] [ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()] Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Acked-by:
Yehuda Yitschak <yehuday@marvell.com> Tested-by:
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