- 19 Jan, 2023 6 commits
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Dmitry Baryshkov authored
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the MMCC device node to be used on APQ8084 platform. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Acked-by:
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Dmitry Baryshkov authored
Define clock/clock-names properties of the GCC device node to be used on APQ8084 platform. Note: the driver uses a single pcie_pipe clock, however most probably there are two pipe clocks, one from each of PCIe QMP PHYs. Acked-by:
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Robert Marko authored
Having only .name populated in parent_data for clocks which are only globally searchable currently will not work as the clk core won't copy that name if there is no .fw_name present as well. So, populate .fw_name for usb3phy clocks in parent_data as they were missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents"). Fixes: ae55ad32 ("clk: qcom: ipq8074: convert to parent data") Signed-off-by:Robert Marko <robimarko@gmail.com> Reviewed-by:
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- 18 Jan, 2023 4 commits
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Bjorn Andersson authored
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Neil Armstrong authored
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Shazad Hussain authored
Add support for the Global Clock Controller found in the QTI SA8775P platforms. Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: made the driver ready for upstream] Co-developed-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by:
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Bartosz Golaszewski authored
Add DT bindings for the GCC clock on SA8775P platforms. Add relevant DT include definitions as well. Signed-off-by:
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- 17 Jan, 2023 5 commits
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Bryan O'Donoghue authored
The XO crystal input is buffered through the PMIC and controlled by RPM. Create the relevant clock gate representation in the RPM clock definitions. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Arnd Bergmann authored
One of the ones that were recently added was already there: drivers/clk/qcom/clk-rpmh.c:578:35: error: initialized field overwritten [-Werror=override-init] 578 | [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, Fixes: aa055bf1 ("clk: qcom: rpmh: define IPA clocks where required") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Krzysztof Kozlowski authored
Add clocks and properties (power-domains, required-opps) already used in SM8250 DTS: sm8250-hdk.dtb: clock-controller@ad00000: clocks: [[46, 10], [44, 0], [44, 1], [45]] is too long sm8250-hdk.dtb: clock-controller@ad00000: clock-names:0: 'bi_tcxo' was expected sm8250-hdk.dtb: clock-controller@ad00000: 'power-domains', 'required-opps' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
Different SoCs come with a bit different clock inputs: sm8250-mtp.dtb: clock-controller@abf0000: clock-names:0: 'bi_tcxo' was expected sm8250-mtp.dtb: clock-controller@abf0000: clock-names: ['iface', 'bi_tcxo', 'bi_tcxo_ao'] is too long Signed-off-by:
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Bjorn Andersson authored
With the transition of disabling unused clocks at sync_state, rather than late_initcall() it's now possible to drop clk_ignore_unused and unused clock disabled once client drivers have probed. Do this on SC8280XP. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # sc8280xp-lenovo-thinkpad-x13s Acked-by:
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- 11 Jan, 2023 25 commits
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Dmitry Baryshkov authored
Follow the example of sc7180 and sdx55 and implement IP0 resource as clocks rather than interconnects. Signed-off-by:
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Konrad Dybcio authored
There's no reason for it not to be static, and some compilers don't like not it being that way. Make it so. Reported-by:
kernel test robot <lkp@intel.com> Fixes: 80f5451d ("clk: qcom: Add camera clock controller driver for SM6350") Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long. Fix that. Signed-off-by:
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Dmitry Baryshkov authored
gcc-msm8974 uses the registered sleep_clk_src clock, which is just a 1:1 fixed factor clock register on top of the board's sleep_clk. Switch the driver to use the board sleep_clk directly. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Reviewed-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Reviewed-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Krzysztof Kozlowski authored
There is no user of core_bi_pll_test_se test clock so drop it. Signed-off-by:
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Krzysztof Kozlowski authored
There is no user of core_bi_pll_test_se test clock so drop it. Signed-off-by:
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Krzysztof Kozlowski authored
Drop unused core_bi_pll_test_se clock input to the clock controller. Signed-off-by:
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Krzysztof Kozlowski authored
Convert Qualcomm SPMI PMIC clock divider bindings to DT schema. Signed-off-by:
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Dmitry Baryshkov authored
The clk-spmi-pmic-div driver gets the parent name from the first (and the only) clock parent. So, use parent data, index 0 to setup the clock. Signed-off-by:
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Dmitry Baryshkov authored
Change gpll0 to use parent_hws instead of parent_names for gcc_disp_gpll0_div_clk_src clock. Signed-off-by:
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Dmitry Baryshkov authored
Rework disp_cc_mdss_rot_clk to use parent_hws instead of parent_names. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using the devm_pm_runtime_enable() instead of hand-coding corresponding action to call pm_runtime_disable(). Signed-off-by:
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Dmitry Baryshkov authored
Switch to using the devm_pm_runtime_enable() instead of hand-coding corresponding action to call pm_runtime_disable(). Signed-off-by:
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