- 09 Nov, 2022 40 commits
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Ben Skeggs authored
Match RM. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Reviewed-by:
Lyude Paul <lyude@redhat.com>
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Ben Skeggs authored
Essentially ripped verbatim from NVGPU, comments and all, and adapted to nvkm's structs and style. - maybe fixes an nvgpu bug though, a small tweak was needed to match RM v2: - remove unnecessary WARN_ON Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
We'll want to reuse the former for loading from proper netlist images. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
We're going to be pulling in a chunk of code from NVGPU to fixup our SMID mappings on Volta and above, which depends on ppc_nr[gpc] reflecting the actual number of PPCs present, not the maximum number. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
This doesn't fix any known issue, but RM started doing it at some point, so presumably it's needed for something. Signed-off-by:
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Ben Skeggs authored
Signed-off-by:
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Ben Skeggs authored
This won't work on Ampere, and, it's questionable whether we should have been using our FW's method of storing the golden context image with NV's firmware to begin with. Signed-off-by:
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Ben Skeggs authored
This doesn't work on Ampere for some reason, switch to directly modifying NV_PGRAPH_FECS_CTXSW_MAILBOX instead. Signed-off-by:
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Ben Skeggs authored
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support - this is saving a *sizeable* amount of vram v2: - whitespace Signed-off-by:
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Ben Skeggs authored
Signed-off-by:
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Ben Skeggs authored
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support Signed-off-by:
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Ben Skeggs authored
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support Signed-off-by:
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Ben Skeggs authored
Needed for GV100 (and only GV100 for some reason) for WFI_GOLDEN_SAVE. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
Needed to support Ampere differences in gr/gf100-: Signed-off-by:
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Ben Skeggs authored
These differ on Ampere. Signed-off-by:
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Ben Skeggs authored
Will be used to improve gr reset on GF100 and newer. Signed-off-by:
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Ben Skeggs authored
- useful to distinguish between different issues. Signed-off-by:
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Ben Skeggs authored
Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by:
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Ben Skeggs authored
Under memory load, instmem allocations could end up in the regions of VRAM that are inaccessible right after boot, and be corrupted after a suspend/resume cycle as a result of being restored before booting the mem unlock firmware. Signed-off-by:
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Ben Skeggs authored
- also executes pre-DEVINIT, so early boot is able to DMA sysmem Signed-off-by:
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Ben Skeggs authored
Adds the start of common interfaces to load and boot the HS binaries provided by NVIDIA that enable the usage of GR. ACR already handles most of this, but it's very much tied into ACR's init process, and there's other code that could benefit from reusing a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber). The VPR scrubber code is fairly independent, and a good first target. - adds better debug output to fw loading process, to ease bring-up/debug v2: - whitespace, 0->false Signed-off-by:
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Ben Skeggs authored
Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
Reset regs won't be available on Ampere while SEC2 RTOS is running, and we're apparently supposed to be doing this on earlier GPUs too. v2: - fixed some excessive indentation Signed-off-by:
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Ben Skeggs authored
Cleanup before falcon changes. Signed-off-by:
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Ben Skeggs authored
Cleanup before falcon changes. - fixes (attempt at?) reset of pmu while rtos is running, on gm20b v2: - remove extra whitespace Signed-off-by:
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Ben Skeggs authored
Cleanup before falcon changes. Signed-off-by:
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Ben Skeggs authored
Ampere. Signed-off-by:
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Ben Skeggs authored
- replaces the hacked-up version that existed solely to support TTM v2. remove earlier hack preventing use of non-stall intr for fences Signed-off-by: -
Ben Skeggs authored
- replaces the hacked-up version that existed solely to support TTM - noop until the next commit, adding proper support for ampere host v2. fixup for ga103 early merge Signed-off-by: -
Ben Skeggs authored
Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by:
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