Merge tag 'imx-legacy-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Pull "i.MX legacy board file changes for 4.9" from Shawn Guo:

It includes a patch series that moves registrations and initializations
of all peripherals which are GPIO line consumers for all legacy boards
from .init_machine to .init_late init level. This is needed to
proactively prevent boot time issues on the legacy boards due to the
deprioritized init level of the GPIO controller driver (set lower than
IOMUX controller driver init level), which is shared among all i.MX
SoCs.

* tag 'imx-legacy-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx legacy: pca100: move peripheral initialization to .init_late
  ARM: imx legacy: mx27ads: move peripheral initialization to .init_late
  ARM: imx legacy: mx21ads: move peripheral initialization to .init_late
  ARM: imx legacy: pcm043: move peripheral initialization to .init_late
  ARM: imx legacy: mx35-3ds: move peripheral initialization to .init_late
  ARM: imx legacy: mx27-3ds: move peripheral initialization to .init_late
  ARM: imx legacy: imx27-visstrim-m10: move peripheral initialization to .init_late
  ARM: imx legacy: vpr200: move peripheral initialization to .init_late
  ARM: imx legacy: mx31moboard: move peripheral initialization to .init_late
  ARM: imx legacy: armadillo5x0: move peripheral initialization to .init_late
  ARM: imx legacy: qong: move peripheral initialization to .init_late
  ARM: imx legacy: mx31-3ds: move peripheral initialization to .init_late
  ARM: imx legacy: pcm037: move peripheral initialization to .init_late
  ARM: imx legacy: mx31lilly: move peripheral initialization to .init_late
  ARM: imx legacy: mx31ads: move peripheral initialization to .init_late
  ARM: imx legacy: mx31lite: move peripheral initialization to .init_late
  ARM: imx legacy: kzm: move peripheral initialization to .init_late

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The change moves some of peripheral registrations and initializations
(all peripherals dependent on GPIOs) from .init_machine to .init_late
level, this allows to safely shift the shared GPIO controller driver
initialization level after init level of i.MX IOMUXC driver.

The change is tested on qemu kzm target.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add a new list address in the MAINTAINERS file for the Oxnas platform.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'uniphier-soc-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/soc

Pull "UniPhier ARM SoC updates for v4.9" from Masahiro Yamada:

* Remove unneeded SMP code

* tag 'uniphier-soc-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: uniphier: remove SoC-specific SMP code

Merge tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Pull "i.MX SoC updates for 4.9" from Shawn Guo:

 - Set INT_MEM_CLK_LPM bit to get proper WAIT mode support on i.MX6SX.
   This is a workaround for i.MX6SX WAIT mode hardware issue.
 - Enable cpuidle support with 3 low-power states (WFI, WAIT, POWER-OFF)
   for i.MX6UL.

* tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: build cpuidle-imx6sx.o for imx6ul
  ARM: imx: add cpuidle support for i.mx6ul
  ARM: imx: enable WAIT mode hardware workaround for imx6sx
  ARM: imx: rename imx6q_set_int_mem_clk_lpm() function

Merge tag 'sunxi-core-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc

Pull "Allwinner core changes for 4.9" from Maxime Ripard:

Add support for big endian on the Allwinner A20, and the Nextthing GR8 SoC

* tag 'sunxi-core-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  ARM: sunxi: Support the Nextthing GR8
  ARM: sunxi: enable big-endian

Pull "This is the pxa changes for v4.9 cycle" from Robert Jarzmik:

This cycle is covering :
 - the removal of the legacy DMA API
   This is the major contributor to the negative diffstat, as dmaengine
   have taken over in this area.
 - IDE subsystem defconfig fixes
 - preparation for pxa25x to be device-tree compliant
 - various irq related fixes

* tag 'pxa-for-4.9' of https://github.com/rjarzmik/linux:
  ARM: pxa: pxa_cplds: fix interrupt handling
  ARM: pxa: remove irq init from dt machines
  ARM: pxa: Use kmalloc_array() in pxa_pm_init()
  ARM: pxa: magician: Remove duplicated I2C pins declaration
  ARM: pxa: fix GPIO double shifts
  arm: trizeps4_defconfig: disable IDE subsystem
  arm: pxa255-idp_defconfig: disable IDE subsystem
  arm: lpda270_defconfig: disable IDE subsystem
  arm: colibri_pxa270_defconfig: disable IDE subsystem
  ARM: pxa: add pxa25x device-tree support
  ARM: pxa: prepare pxa25x interrupts for device-tree platforms
  ARM: pxa: remove platform dma code
  ARM: pxa: remove devicetree boards from pxa_defconfig

Merge tag 'renesas-soc-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Pull "Renesas ARM Based SoC Updates for v4.9" from Simon Horman:

Clean-up:
* Only use smp_init when SMP is selected

Enablement:
* Add debug-ll support for r8a7992

* tag 'renesas-soc-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7791: only use smp_init when SMP is selected
  ARM: shmobile: r8a7790: only use smp_init when SMP is selected
  ARM: debug-ll: Add support for r8a7992

Pull "Broadcom soc changes for 4.9" from Florian Fainelli:

This pull request contains Broadcom ARM-based SoC changes for 4.9, please pull
the following:

- Rafal adds preliminary support for the new BCM53573 Wi-Fi SoC based on a
  single core Cortex A7 and re-using a bunch of iProc peripherals

- Florian adds support for earlyprintk on Broadcom STB/CM ARM-based chips by
  reading the chip family_id value from a known location and deriving the UART
  based address

* tag 'arm-soc/for-4.9/soc' of http://github.com/Broadcom/stblinux:
  ARM: BCM53573: Initial support for Broadcom BCM53573 SoCs
  ARM: brcmstb: Add earlyprintk support using run-time checks

Merge tag 'qcom-soc-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/soc

Pull "Qualcomm ARM Based SoC Updates for v4.9" from Andy Gross:

* Remove unnecessary QCOM board file

* tag 'qcom-soc-for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  ARM: qcom: Cleanup/Remove unnecessary board file

Since its initial commit, the driver is buggy for multiple interrupts
handling. The translation from the former lubbock.c file was not
complete, and might stall all interrupt handling when multiple
interrupts occur.

This is especially true when inside the interrupt handler and if a new
interrupt comes and is not handled, leaving the output line still held,
and not creating a transition as the GPIO block behind would expect to
trigger another cplds_irq_handler() call.

For the record, the hardware is working as follows.

The interrupt mechanism relies on :
 - one status register
 - one mask register

Let's suppose the input irq lines are called :
 - i_sa1111
 - i_lan91x
 - i_mmc_cd
Let's suppose the status register for each irq line is called :
 - status_sa1111
 - status_lan91x
 - status_mmc_cd
Let's suppose the interrupt mask for each irq line is called :
 - irqen_sa1111
 - irqen_lan91x
 - irqen_mmc_cd
Let's suppose the output irq line, connected to GPIO0 is called :
 - o_gpio0

The behavior is as follows :
 - o_gpio0 = not((status_sa1111 & irqen_sa1111) |
		 (status_lan91x & irqen_lan91x) |
		 (status_mmc_cd & irqen_mmc_cd))
   => this is a N-to-1 NOR gate and multiple AND gates
 - irqen_* is exactly as programmed by a write to the FPGA
 - status_* behavior is governed by a bi-stable D flip-flop
   => on next FPGA clock :
     - if i_xxx is high, status_xxx becomes 1
     - if i_xxx is low, status_xxx remains as it is
     - if software sets status_xxx to 0, the D flip-flop is reset
       => status_xxx becomes 0
       => on next FPGA clock cycle, if i_xxx is high, status_xxx becomes
	  1 again

Fixes: fc9e38c0 ("ARM: pxa: lubbock: use new pxa_cplds driver")
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

The init_irq and handle_irq can be declared through standard irqchip
declaration and are not necessary in machine descriptions.

This is another step towards the generic kernel for the pxa
architecture.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Arnd Bergmann <arnd@arndb.de>

* A multiplication for the size determination of a memory allocation
  indicated that an array data structure should be processed.
  Thus use the corresponding function "kmalloc_array".

  This issue was detected by using the Coccinelle software.

* Replace the specification of a data type by a pointer dereference
  to make the corresponding size determination a bit safer according to
  the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

Magician has GPIO117_I2C_SCL and GPIO118_I2C_SDA pins declared twice.
Signed-off-by: Petr Cvek <petr.cvek@tul.cz>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

The commit 9bf448c6 ("ARM: pxa: use generic gpio operation instead of
gpio register") from Oct 17, 2011, leads to the following static checker
warning:
  arch/arm/mach-pxa/spitz_pm.c:172 spitz_charger_wakeup()
  warn: double left shift '!gpio_get_value(SPITZ_GPIO_KEY_INT)
        << (1 << ((SPITZ_GPIO_KEY_INT) & 31))'

As Dan reported, the value is shifted three times :
 - once by gpio_get_value(), which returns either 0 or BIT(gpio)
 - once by the shift operation '<<'
 - a last time by GPIO_bit(gpio) which is BIT(gpio)

Therefore the calculation lead to a chained or operator of :
 - (1 << gpio) << (1 << gpio) = (2^gpio)^gpio = 2 ^ (gpio * gpio)

It is be sheer luck the former statement works, only because each gpio
used is strictly smaller than 6, and therefore 2^(gpio^2) never
overflows a 32 bits value, and because it is used as a boolean value to
check a gpio activation.

As the xxx_charger_wakeup() functions are used as a true/false detection
mechanism, take that opportunity to change their prototypes from integer
return value to boolean one.

Fixes: 9bf448c6 ("ARM: pxa: use generic gpio operation instead of
gpio register")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Joe Perches <joe@perches.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>

The imx6ul soc code gained support for cpuidle, but that causes
a link failure if CONFIG_SOC_IMX6SX is disabled:

arch/arm/mach-imx/mach-imx6ul.o: In function `imx6ul_init_late':
mach-imx6ul.c:(.init.text+0xc): undefined reference to `imx6sx_cpuidle_init'

This adds the file containing the imx6sx_cpuidle_init function
to the kernel for 6ul-only configurations.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 547e8f52 ("ARM: imx: add cpuidle support for i.mx6ul")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.

It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
but some controllers missing too (Ethernet, less I2C, less UARTs).
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Merge tag 'samsung-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc

Merge "Samsung mach/soc update for v4.9" from Krzysztof Kozlowski:

1. Fix for DMA on S3C24xx. This was probably broken for long time, nobody runs
   this code... till now.
2. After fixes from Matthew Leach and Ben Dooks, most of our mach code
   and drivers is now endian-safe. Mark the platform as supporting big endian.
3. Cleanups.

* tag 'samsung-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: EXYNOS: Remove unused DMC and CMU offsets and their mappings
  ARM: s3c64xx: Delete unnecessary assignment for the field "owner"
  ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly
  ARM: S3C24XX: Add missing DMA device for Mini2440 board
  ARM: S3C24XX: Add dma_mask assignments for DMA devices

Merge tag 'davinci-for-v4.9/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

Merge "DaVinci soc support updates for v4.9" from Sekhar Nori:

DA850 SoC support update for making it possible
to use TI AEMIF driver in drivers/memory on DA850.

* tag 'davinci-for-v4.9/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: da850: Add ti-aemif lookup for clock matching

This patch enables cpuidle driver for i.MX6UL, it
reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle
supported:

1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.

As i.MX6UL has cortex-A7 CORE with an internal L2
cache, so flushing it before powering down ARM platform
is necessary, flush_cache_all() in last step of cpu_suspend
has very small overhead, just call it to avoid cache
type check for different platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Need to enable INT_MEM_CLK_LPM bit in CCM_CGPR for WAIT mode,
without this bit set, if there is pending interrupt during
ARM platform entering WAIT mode without power gating, cache
data will be corrupted, this is a hardware workaround for WAIT
mode and must be enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Let's rename the function imx6q_set_int_mem_clk_lpm()
to imx6_set_int_mem_clk_lpm() since it's actually
common for all i.MX6 SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Pull drm fixes from Dave Airlie:
 "A bunch of fixes covering i915, amdgpu, one tegra and some core DRM
  ones.  Nothing too strange at this point"

* tag 'drm-fixes-for-4.8-rc4' of git://people.freedesktop.org/~airlied/linux: (21 commits)
  drm/atomic: Don't potentially reset color_mgmt_changed on successive property updates.
  drm: Protect fb_defio in drivers with CONFIG_KMS_FBDEV_EMULATION
  drm/amdgpu: skip TV/CV in display parsing
  drm/amdgpu: avoid a possible array overflow
  drm/amdgpu: fix lru size grouping v2
  drm/tegra: dsi: Enhance runtime power management
  drm/i915: Fix botched merge that downgrades CSR versions.
  drm/i915/skl: Ensure pipes with changed wms get added to the state
  drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
  drm/i915/skl: Add support for the SAGV, fix underrun hangs
  drm/i915/gen6+: Interpret mailbox error flags
  drm/i915: Reattach comment, complete type specification
  drm/i915: Unconditionally flush any chipset buffers before execbuf
  drm/i915/gen9: Drop invalid WARN() during data rate calculation
  drm/i915/gen9: Initialize intel_state->active_crtcs during WM sanitization (v2)
  drm: Reject page_flip for !DRIVER_MODESET
  drm/amdgpu: fix timeout value check in amd_sched_job_recovery
  drm/amdgpu: fix sdma_v2_4_ring_test_ib
  drm/amdgpu: fix amdgpu_move_blit on 32bit systems
  drm/radeon: fix radeon_move_blit on 32bit systems
  ...