- 07 Oct, 2020 2 commits
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Geert Uytterhoeven authored
The Toshiba Visconti TMPV7700 series pin controller is only present on Visconti SoCs. Hence add a dependency on ARCH_VISCONTI, to prevent asking the user about this driver when configuring a kernel without Visconti platform support. Fixes: a68a7844 ("pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20201005125049.26926-1-geert+renesas@glider.beSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Enric Balletbo i Serra authored
The pinctrl driver can work without the EINT resource, but, if it is expected to have this resource but the mtk_build_eint() function fails after allocating their data (because can't get the resource or can't map the irq), the data is not freed and you end with a NULL pointer dereference. Fix this by freeing the data if mtk_build_eint() fails, so pinctrl still works and doesn't hang. This is noticeable after commit f97dbf48 ("irqchip/mtk-sysirq: Convert to a platform driver") on MT8183 because, due this commit, the pinctrl driver fails to map the irq and spots the following bug: [ 1.947597] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000004 [ 1.956404] Mem abort info: [ 1.959203] ESR = 0x96000004 [ 1.962259] EC = 0x25: DABT (current EL), IL = 32 bits [ 1.967565] SET = 0, FnV = 0 [ 1.970613] EA = 0, S1PTW = 0 [ 1.973747] Data abort info: [ 1.976619] ISV = 0, ISS = 0x00000004 [ 1.980447] CM = 0, WnR = 0 [ 1.983410] [0000000000000004] user address but active_mm is swapper [ 1.989759] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 1.995322] Modules linked in: [ 1.998371] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc1+ #44 [ 2.004715] Hardware name: MediaTek krane sku176 board (DT) [ 2.010280] pstate: 60000005 (nZCv daif -PAN -UAO BTYPE=--) [ 2.015850] pc : mtk_eint_set_debounce+0x48/0x1b8 [ 2.020546] lr : mtk_eint_set_debounce+0x34/0x1b8 [ 2.025239] sp : ffff80001008baa0 [ 2.028544] x29: ffff80001008baa0 x28: ffff0000ff7ff790 [ 2.033847] x27: ffff0000f9ec34b0 x26: ffff0000f9ec3480 [ 2.039150] x25: ffff0000fa576410 x24: ffff0000fa502800 [ 2.044453] x23: 0000000000001388 x22: ffff0000fa635f80 [ 2.049755] x21: 0000000000000008 x20: 0000000000000000 [ 2.055058] x19: 0000000000000071 x18: 0000000000000001 [ 2.060360] x17: 0000000000000000 x16: 0000000000000000 [ 2.065662] x15: ffff0000facc8470 x14: ffffffffffffffff [ 2.070965] x13: 0000000000000001 x12: 00000000000000c0 [ 2.076267] x11: 0000000000000040 x10: 0000000000000070 [ 2.081569] x9 : ffffaec0063d24d8 x8 : ffff0000fa800270 [ 2.086872] x7 : 0000000000000000 x6 : 0000000000000011 [ 2.092174] x5 : ffff0000fa800248 x4 : ffff0000fa800270 [ 2.097476] x3 : ffff8000100c5000 x2 : 0000000000000000 [ 2.102778] x1 : 0000000000000000 x0 : 0000000000000000 [ 2.108081] Call trace: [ 2.110520] mtk_eint_set_debounce+0x48/0x1b8 [ 2.114870] mtk_gpio_set_config+0x5c/0x78 [ 2.118958] gpiod_set_config+0x5c/0x78 [ 2.122786] gpiod_set_debounce+0x18/0x28 [ 2.126789] gpio_keys_probe+0x50c/0x910 [ 2.130705] platform_drv_probe+0x54/0xa8 [ 2.134705] really_probe+0xe4/0x3b0 [ 2.138271] driver_probe_device+0x58/0xb8 [ 2.142358] device_driver_attach+0x74/0x80 [ 2.146532] __driver_attach+0x58/0xe0 [ 2.150274] bus_for_each_dev+0x70/0xc0 [ 2.154100] driver_attach+0x24/0x30 [ 2.157666] bus_add_driver+0x14c/0x1f0 [ 2.161493] driver_register+0x64/0x120 [ 2.165319] __platform_driver_register+0x48/0x58 [ 2.170017] gpio_keys_init+0x1c/0x28 [ 2.173672] do_one_initcall+0x54/0x1b4 [ 2.177499] kernel_init_freeable+0x1d0/0x238 [ 2.181848] kernel_init+0x14/0x118 [ 2.185328] ret_from_fork+0x10/0x34 [ 2.188899] Code: a9438ac1 12001266 f94006c3 121e766a (b9400421) [ 2.194991] ---[ end trace 168cf7b3324b6570 ]--- [ 2.199611] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 2.207260] SMP: stopping secondary CPUs [ 2.211294] Kernel Offset: 0x2ebff4800000 from 0xffff800010000000 [ 2.217377] PHYS_OFFSET: 0xffffb50500000000 [ 2.221551] CPU features: 0x0240002,2188200c [ 2.225811] Memory Limit: none [ 2.228860] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]--- Fixes: 89132dd8 ("pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c") Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20201001142511.3560143-1-enric.balletbo@collabora.com [rebased on changed infrastructure] Signed-off-by:
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- 01 Oct, 2020 2 commits
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Drew Fustini authored
The debug output in pcs_parse_one_pinctrl_entry() needs to be updated to print the correct pinctrl register value when #pinctrl-cells is 2. Fixes: a1339541 ("pinctrl: single: parse #pinctrl-cells = 2") Reported-by:
Trent Piepho <tpiepho@gmail.com> Signed-off-by:
Drew Fustini <drew@beagleboard.org> Acked-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200913230306.2061645-1-drew@beagleboard.orgSigned-off-by:
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Drew Fustini authored
The property #pinctrl-cells can either be 1 or 2: - if #pinctrl-cells = <1>, then pinctrl_spec.args_count = 2 - if #pinctrl-cells = <2>, then pinctrl_spec.args_count = 3 All other values of pinctrl_spec.args_count are incorrect. This fix checks the upper bound instead of just the lower bound. Fixes: a1339541 ("pinctrl: single: parse #pinctrl-cells = 2") Reported-by:
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- 30 Sep, 2020 6 commits
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Andy Shevchenko authored
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20200929110306.40852-3-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended. Signed-off-by:
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Andy Shevchenko authored
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant. Fixes: 653d9645 ("pinctrl: tigerlake: Add support for Tiger Lake-H") Reported-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by:
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Drew Fustini authored
Document the values in pinctrl-single,pins when #pinctrl-cells = <2> Fixes: 27c90e5e ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") Reported-by:
Rob Herring <robh@kernel.org> Acked-by:
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Wang Xiaojun authored
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by:
Wang Xiaojun <wangxiaojun11@huawei.com> Acked-by:
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Rikard Falkeborn authored
The only usage of these structs is to assign their address to various ops fields in the pinctrl_desc struct, which are const pointers. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200926202342.31014-1-rikard.falkeborn@gmail.comSigned-off-by:
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- 29 Sep, 2020 17 commits
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Chuanhong Guo authored
These pins are named ANTSEL[0~29] in datasheet and are used by wmac for various functions. Signed-off-by:
Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200922164159.120920-1-gch981213@gmail.comSigned-off-by:
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Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Link: https://lore.kernel.org/r/20200921131057.92895-1-miaoqinglang@huawei.comSigned-off-by:
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Eugen Hristev authored
Add support for sama7g5 pinctrl block, which has 5 PIO banks. Signed-off-by:
Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200917131257.273882-2-eugen.hristev@microchip.comSigned-off-by:
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Eugen Hristev authored
Add compatible string for microchip sama7g5 SoC. Signed-off-by:
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Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20200921131058.92941-1-miaoqinglang@huawei.comSigned-off-by:
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Liu Shixin authored
Simplify the return expression. Signed-off-by:
Liu Shixin <liushixin2@huawei.com> Acked-by:
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Liu Shixin authored
module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by:
Chunyan Zhang <zhang.lyra@gmail.com> Link: https://lore.kernel.org/r/20200914065402.3726408-1-liushixin2@huawei.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Add I2S pins support for the JZ4780 SoC. 2.Add I2S pins support for the X1000 SoC. 3.Add I2S pins support for the X1500 SoC. 4.Add I2S pins support for the X1830 SoC. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.comSigned-off-by:
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周琰杰 (Zhou Yanjie) authored
Correct the pullup and pulldown parameters of JZ4780 to make them consistent with the parameters on the datasheet. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add SSI pins support for the JZ4770 SoC and the JZ4780 SoC from Ingenic. Signed-off-by:
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Andrew Jeffery authored
These were skipped in the original patches adding pinconf support for the AST2600. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Reviewed-by:
Joel Stanley <joel@jms.id.au> Cc: Johnny Huang <johnny_huang@aspeedtech.com> Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.auSigned-off-by:
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Andrew Jeffery authored
The Aspeed pinconf data structures are split into 'conf' and 'map' types, where the 'conf' struct defines which register and bitfield to manipulate, while the 'map' struct defines what value to write to the register and bitfield. Both structs have a mask member, and the wrong mask was being used to tell the regmap which bits to update. A todo is to look at whether we can remove the mask from the 'map' struct. Fixes: 5f52c853 ("pinctrl: aspeed: Use masks to describe pinconf bitfields") Signed-off-by:
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Andrew Jeffery authored
When displaying which pinconf register and field is being touched, format the field mask so that it's consistent with the way the pinmux portion formats the mask. Signed-off-by:
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Krzysztof Kozlowski authored
The convention for node names is to use hyphens, not underscores. dtschema expects GPIO hogs to end with 'hog' suffix. Adjust the example DTS in the binding. No changes to binding itself. Reported-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200928184515.7345-1-krzk@kernel.orgSigned-off-by:
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Anson Huang authored
Change PINCTRL_IMX to tristate to support loadable module build. And i.MX common pinctrl driver should depend on CONFIG_OF to make sure no build error when i.MX common pinctrl driver is enabled for different architectures without CONFIG_OF. Also add module author, description and license. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1599552721-24872-3-git-send-email-Anson.Huang@nxp.comSigned-off-by:
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Anson Huang authored
Change PINCTR_IMX_SCU to tristate, add module author, description and license to support building SCU pinctrl core driver as module. Signed-off-by:
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Anson Huang authored
Use function callbacks for SCU related functions in pinctrl-imx.c in order to support the scenario of PINCTRL_IMX is built in while PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl driver need to initialize the SCU related function callback, and no need to check CONFIG_PINCTRL_IMX_SCU anymore, hence stub functions also can be removed. Signed-off-by:
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- 27 Sep, 2020 2 commits
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Fabien Parent authored
This commit adds the pinctrl driver for the MediaTek's MT8167 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200907110221.1691168-2-fparent@baylibre.comSigned-off-by:
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Fabien Parent authored
Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by:
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- 21 Sep, 2020 2 commits
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.10-1 * Add last part of cleanup Cherryview driver to align with other drivers * Due to above clean up Cherryview and Baytrail drivers to use common API The following is an automated git shortlog grouped by driver: baytrail: - Switch to use intel_pinctrl_get_soc_data() cherryview: - Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs - Switch to use intel_pinctrl_get_soc_data() - Utilize temporary variable to hold device pointer - Switch to use struct intel_pinctrl - Move custom community members to separate data struct - Drop stale comment intel: - Update header block to reflect direct dependencies - Extract intel_pinctrl_get_soc_data() helper for wider use
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.10 - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1, - Three more conversion of DT bindings to json-schema, - Group all Renesas pinctrl drivers and improve visual Kconfig structure, - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, - Minor fixes and improvements.
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- 15 Sep, 2020 9 commits
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Geert Uytterhoeven authored
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by: -
Geert Uytterhoeven authored
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by:
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Geert Uytterhoeven authored
The RZ/N1 pin control driver does not use pin groups or pin functions, so there is no need to select GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. Signed-off-by:
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Geert Uytterhoeven authored
Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
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Geert Uytterhoeven authored
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by:
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Geert Uytterhoeven authored
For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 42556242 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Acked-by:
Jacopo Mondi <jacopo@jmondi.org> Acked-by:
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Kuninori Morimoto authored
Sort each driver by description title in alphabetical order. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87h7ssy4qy.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
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Kuninori Morimoto authored
Now, Renesas Pin Control drivers are under menu, but current descriptions are not aligned. This patch aligns them. - RZ/A2 gpio and pinctrl driver - RZ/N1 pinctrl driver - Emma Mobile EV2 pin control support - R-Mobile APE6 pin control support - R-Mobile A1 pin control support - RZ/G1H pin control support - RZ/G1M pin control support + pin control support for RZ/A2 + pin control support for RZ/N1 + pin control support for Emma Mobile EV2 + pin control support for R-Mobile APE6 + pin control support for R-Mobile A1 + pin control support for RZ/G1H + pin control support for RZ/G1M Signed-off-by:
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