- 11 Dec, 2007 25 commits
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Stephen Rothwell authored
so remove a firmware feature test. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Stephen Rothwell authored
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Stephen Rothwell authored
and it becomes clear that we should use zalloc_maybe_bootmem. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
and an unnecessary cast. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
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Stephen Rothwell authored
Also remove another unnecessary forward declaration. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
No semantic changes. Signed-off-by:
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Stephen Rothwell authored
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Stephen Rothwell authored
It only needs the iommu_table address. It also makes use of the node name to print error messages. So just pass it the things it needs. This reduces the places that know about the pci_dn by one. Signed-off-by:
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Nathan Lynch authored
The 'data' member of proc_ppc64_lparcfg is unused, but the lparcfg module's init routine allocates 4K for it. Remove the code which allocates and frees this buffer. Signed-off-by:
Nathan Lynch <ntl@pobox.com> Signed-off-by:
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Ishizaki Kou authored
Signed-off-by:
Kou Ishizaki <Kou.Ishizaki@toshiba.co.jp> Signed-off-by:
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Ishizaki Kou authored
This adds support for native CBE on Celleb, that is, without the BEAT hypervisor. Many codes in platforms/cell/ are used in native CBE environment. Signed-off-by:
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Ishizaki Kou authored
This fixes the following link error with CONFIG_PPC_CELL_NATIVE=y and CONFIG_PPC_CELL_BLADE=n: arch/powerpc/platforms/built-in.o: In function `.cell_setup_arch': setup.c:(.init.text+0xe80): undefined reference to `.mmio_nvram_init' Signed-off-by:
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Stephen Rothwell authored
so consolidate it into misc.S. Signed-off-by:
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Michael Ellerman authored
Add for_each_child_of_node() to encapsulate the common idiom of iterating over the children of a device_node. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Acked-by:
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Stephen Rothwell authored
Also use of_unregister_driver to implement of_unregister_platform_driver. Signed-off-by:
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- 10 Dec, 2007 1 commit
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Paul Mackerras authored
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- 07 Dec, 2007 14 commits
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Linus Torvalds authored
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev: libata: kill spurious NCQ completion detection ahci: don't attach if ICH6 is in combined mode ata_piix: add Toshiba Tecra M4 to broken suspend list ahci: fix engine reset failed message
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Tejun Heo authored
Spurious NCQ completion detection implemented in ahci was incorrect. On AHCI receving and processing FISes and raising interrupts are not interlocked and spurious interrupts are expected. For example, if an interrupt occurs while interrupt handler is running and the running interrupt handler handles the event the new IRQ indicated, after IRQ handler finishes, it will be executed again because IRQ pending bit is set by the new interrupt but there won't be anything to process. Please read the following message for more information. http://article.gmane.org/gmane.linux.ide/26012 This patch... * Removes all spurious IRQ whining from ahci. Spurious NCQ completion detection was completely wrong. Spurious D2H Register FIS taught us that some early drives send spurious D2H Register FIS with I bit set while NCQ commands are in progress but none of recent drives does that and even the ones which show such behavior can do NCQ fine. * Kills all NCQ blacklist entries which were added because of spurious NCQ completions. I tracked down each commit and verified all removed ones are actually added because of spurious completions. WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive not only had spurious NCQ completions but also is slow on sequential data transfers if NCQ is enabled. Maxtor 7V300F0 was added by 0e3dbc01 from Alan Cox. I can only find evidences that the drive only had troubles with spuruious completions by searching the mailing list. This entry needs to be verified and removed if it doesn't have other NCQ related problems. Signed-off-by:
Tejun Heo <htejun@gmail.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by:
Jeff Garzik <jeff@garzik.org>
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Tejun Heo authored
ICH6 R/Ms share PCI ID between piix and ahci modes and we've been allowing ahci to attach regardless of how BIOS configured it. However, enabling AHCI mode when the controller is in combined mode can result in unexpected behavior. Don't attach if the controller is in combined mode. Signed-off-by:
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Peter Schwenke authored
Add Toshiba Tecra M4 to broken suspend list. This is from OSDL bugzilla bug 7780. Signed-off-by:
Peter Schwenke <peter@bluetoad.com.au> Signed-off-by:
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Tejun Heo authored
There isn't much point in reporting -EOPNOTSUPP as failure. Also the message was missing newline. Signed-off-by:
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Sreenivasa Honnur authored
- Making sure register initialisation is complete before proceeding further. The driver must wait until initialization is complete before attempting to access any other device registers. Signed-off-by:
Surjit Reang <surjit.reang@neterion.com> Signed-off-by:
Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Signed-off-by:
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Benjamin Herrenschmidt authored
This updates the copyright notices of the new EMAC driver to avoid confusion as who is to be blamed for new bugs. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Valentine Barshak authored
The patch moves dev_set_drvdata(&ofdev->dev, dev) up before tah_reset(ofdev) is called to avoid a NULL pointer dereference, since tah_reset uses drvdata. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
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Valentine Barshak authored
This patch fixes a typo in ibm_newemac/core.c (tah_port should be used instead of tah_ph) Signed-off-by:
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Valentine Barshak authored
The EMAC4_MR1_OBCI(freq) macro expects freg in MHz, while opb_bus_freq is kept in Hz. Correct this. Signed-off-by:
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Hugh Blemings authored
Depending on how the 44x processors are wired, some EMAC cells might not be useable (and not connected to a PHY). However, some device-trees may choose to still expose them (since their registers are present in the MMIO space) but with an "unused" property in them. Signed-off-by:
Hugh Blemings <hugh@blemings.org> Signed-off-by:
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Benjamin Herrenschmidt authored
There are a few variants of the STACR register that affect more than just the "AXON" version of EMAC. Replace the current test of various chip models with tests for generic properties in the device-tree. Signed-off-by:
Stefan Roese <sr@denx.de> Signed-off-by:
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Benjamin Herrenschmidt authored
More than just "AXON" version of EMAC RGMII supports MDIO, so replace the current test with a generic property in the device-tree that indicates such support. Signed-off-by:
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Benjamin Herrenschmidt authored
With some PHYs, when the link goes away, the EMAC reset fails due to the loss of the RX clock I believe. The old EMAC driver worked around that using some internal chip-specific clock force bits that are different on various 44x implementations. This is an attempt at doing it differently, by avoiding the reset when there is no link, but forcing loopback mode instead. It seems to work on my Taishan 440GX based board so far. Signed-off-by:
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