- 09 Dec, 2023 4 commits
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Luca Weiss authored
Enable the UFS phy and controller so that we can access the internal storage of the phone. At the same time we need to bump the minimum voltage used for UFS VCC, otherwise it doesn't initialize properly. The 2.952V is taken from the vcc-voltage-level property downstream. See also the following link for more information about the VCCQ/VCCQ2: https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/1590a3739e7dc29d2597307881553236d492f188/fp5/yupik-idp-pm7250b.dtsi#207Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231002-fp5-ufs-v2-1-e2d7de522134@fairphone.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Luca Weiss authored
The dtbs_check really doesn't like having memory without reg set. The base address depends on the amount of RAM you have: <= 2.00 GiB RAM: 0x80000000 = 3.00 GiB RAM: 0x40000000 = 3.75 GiB RAM: 0x10000000 (more does not fit into the 32-bit physical address space) So, let's pick one of the values, 0x10000000 which is used on devices with 3.75 GiB RAM. Since the bootloader will update it to what's present on the device it doesn't matter too much. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-msm8953-misc-fixes-v2-1-df86655841d9@z3ntu.xyzSigned-off-by:
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Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 IDP board. Signed-off-by:
Nitin Rawat <quic_nitirawa@quicinc.com> Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Nitin Rawat authored
Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by:
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- 08 Dec, 2023 27 commits
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Neil Armstrong authored
Declare the displayport controller present on the Qualcomm SM8650 SoC and connected to the USB3/DP Combo PHY. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-dp-v2-1-69dab3d074e4@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
The address/size cells in PWM node are needed only if individual LEDs are listed. If multi-led is used, then this leads to dtc W=1 warnings: pm8550.dtsi:65.19-73.5: Warning (avoid_unnecessary_addr_size): /soc@0/spmi@c400000/pmic@1/pwm: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208124332.48636-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Abel Vesa authored
Add basic support for X1E80100 CRD board dts, which allows it to boot to a shell. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Rajendra Nayak authored
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU and LLCC nodes. Co-developed-by:
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Rajendra Nayak authored
Document the X1E80100 SoC binding and also the boards using it. Also document the new board id qcp (Qualcomm Compute Platform). Signed-off-by:
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Rajendra Nayak authored
Oryon is the custom ARM CPU core implementation used in Qualcomm's X1E80100 SoC, document it. Signed-off-by:
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Bjorn Andersson authored
Merge branch 'icc-x1e80100' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the X1E80100 interconnect binding to get access to the interconnect port constants.
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Bjorn Andersson authored
Merge the X1E80100 clock bindings to get access to the clock constants.
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Rajendra Nayak authored
Add bindings and update documentation for clock rpmh driver on X1E80100 SoCs. Signed-off-by:
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Rajendra Nayak authored
Add device tree bindings for global clock controller on X1E80100 SoCs. Signed-off-by:
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Krzysztof Kozlowski authored
Add nodes for WSA8845 speakers on SM8650 MTP board. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add nodes for LPASS Soundwire v2.0.0 controllers. Use labels with indices matching downstream DTS, to make any comparisons easier. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8650. The nodes are very similar to SM8550. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the ADSP Generic Packet Router (GPR) device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Enable IPA on the SM8650 QRD. The GSI firmware on this platform is loaded by the AP. Signed-off-by:
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Neil Armstrong authored
Add IPA-related nodes and definitions to SM8650 dtsi, which uses IPA v5.5.1 a minor revision of v5.5 found in the SM8550 SoC. Signed-off-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 QRD board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink - Bluetooth Reviewed-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 MTP board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink Reviewed-by:
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Neil Armstrong authored
Add Hardware nodes that depends on an interconnect property to be valid. The includes: - all QUP i2s/spi nodes - PCIe - UFS - SDHCI - Display - HWMON Acked-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, it supports boot to shell with buttons, leds and USB peripheral. Reviewed-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, only boots to shell with USB device support. Reviewed-by:
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Neil Armstrong authored
The pm8550ve can be found with a different SID on SM8650 platforms, make it configurable. Reviewed-by:
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Neil Armstrong authored
Add initial DTSI for the Qualcomm SM8650 platform, only contains nodes which doesn't depend on interconnect. Reviewed-by:
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Neil Armstrong authored
Document the SM8650 SoC and based MTP (Mobile Test Platforms) and QRD (Qualcomm Reference Device) boards. Reviewed-by:
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Bjorn Andersson authored
Merge branch 'icc-sm8650' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the SM8650 interconnect binding, to gain access to the interconnect port constants.
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Bjorn Andersson authored
Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8 Merge the SM8650 clock bindings, to gain access to the clock constants.
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- 07 Dec, 2023 9 commits
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Luka Panio authored
Initial support for Xiaomi Pad 6 tablet, that have sm8250 soc. Signed-off-by:
Luka Panio <lukapanio@gmail.com> Acked-by:
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Luka Panio authored
Add a compatible for Xiaomi Pad 6. Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Alex Elder authored
Enable IPA on the SM8550 QRD. The GSI firmware on this platform is loaded by the AP. Signed-off-by:
Alex Elder <elder@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20231124181718.915208-3-elder@linaro.orgSigned-off-by:
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Alex Elder authored
Add IPA-related nodes and definitions to "sm8550.dtsi", which uses IPA v5.5. Signed-off-by:
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Sibi Sankar authored
Extend pattern matching to support the X1E platform name. Signed-off-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by:
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Robert Marko authored
Add node to support the QUP4 SPI controller inside of IPQ8074. Some devices use this bus to communicate to a Bluetooth controller. Signed-off-by:
Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.comSigned-off-by:
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Imran Shaik authored
Add device node for ECPRI clock controller on qcom QDU1000 and QRU1000 SoCs. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: 7f7e5c1b ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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