- 30 Sep, 2020 4 commits
-
-
Andy Shevchenko authored
It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant. Fixes: 653d9645 ("pinctrl: tigerlake: Add support for Tiger Lake-H") Reported-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20200929110306.40852-1-andriy.shevchenko@linux.intel.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Drew Fustini authored
Document the values in pinctrl-single,pins when #pinctrl-cells = <2> Fixes: 27c90e5e ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") Reported-by:
Trent Piepho <tpiepho@gmail.com> Signed-off-by:
Drew Fustini <drew@beagleboard.org> Reviewed-by:
Rob Herring <robh@kernel.org> Acked-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200919200836.3218536-1-drew@beagleboard.orgSigned-off-by:
-
Wang Xiaojun authored
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by:
Wang Xiaojun <wangxiaojun11@huawei.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20200917064151.2184010-1-wangxiaojun11@huawei.comSigned-off-by:
-
Rikard Falkeborn authored
The only usage of these structs is to assign their address to various ops fields in the pinctrl_desc struct, which are const pointers. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200926202342.31014-1-rikard.falkeborn@gmail.comSigned-off-by:
-
- 29 Sep, 2020 17 commits
-
-
Chuanhong Guo authored
These pins are named ANTSEL[0~29] in datasheet and are used by wmac for various functions. Signed-off-by:
Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200922164159.120920-1-gch981213@gmail.comSigned-off-by:
-
Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Link: https://lore.kernel.org/r/20200921131057.92895-1-miaoqinglang@huawei.comSigned-off-by:
-
Eugen Hristev authored
Add support for sama7g5 pinctrl block, which has 5 PIO banks. Signed-off-by:
Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200917131257.273882-2-eugen.hristev@microchip.comSigned-off-by:
-
Eugen Hristev authored
Add compatible string for microchip sama7g5 SoC. Signed-off-by:
-
Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20200921131058.92941-1-miaoqinglang@huawei.comSigned-off-by:
-
Liu Shixin authored
Simplify the return expression. Signed-off-by:
Liu Shixin <liushixin2@huawei.com> Acked-by:
-
Liu Shixin authored
module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by:
Chunyan Zhang <zhang.lyra@gmail.com> Link: https://lore.kernel.org/r/20200914065402.3726408-1-liushixin2@huawei.comSigned-off-by:
-
周琰杰 (Zhou Yanjie) authored
1.Add I2S pins support for the JZ4780 SoC. 2.Add I2S pins support for the X1000 SoC. 3.Add I2S pins support for the X1500 SoC. 4.Add I2S pins support for the X1830 SoC. Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.comSigned-off-by:
-
周琰杰 (Zhou Yanjie) authored
Correct the pullup and pulldown parameters of JZ4780 to make them consistent with the parameters on the datasheet. Signed-off-by:
-
周琰杰 (Zhou Yanjie) authored
Add SSI pins support for the JZ4770 SoC and the JZ4780 SoC from Ingenic. Signed-off-by:
-
Andrew Jeffery authored
These were skipped in the original patches adding pinconf support for the AST2600. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Reviewed-by:
Joel Stanley <joel@jms.id.au> Cc: Johnny Huang <johnny_huang@aspeedtech.com> Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.auSigned-off-by:
-
Andrew Jeffery authored
The Aspeed pinconf data structures are split into 'conf' and 'map' types, where the 'conf' struct defines which register and bitfield to manipulate, while the 'map' struct defines what value to write to the register and bitfield. Both structs have a mask member, and the wrong mask was being used to tell the regmap which bits to update. A todo is to look at whether we can remove the mask from the 'map' struct. Fixes: 5f52c853 ("pinctrl: aspeed: Use masks to describe pinconf bitfields") Signed-off-by:
-
Andrew Jeffery authored
When displaying which pinconf register and field is being touched, format the field mask so that it's consistent with the way the pinmux portion formats the mask. Signed-off-by:
-
Krzysztof Kozlowski authored
The convention for node names is to use hyphens, not underscores. dtschema expects GPIO hogs to end with 'hog' suffix. Adjust the example DTS in the binding. No changes to binding itself. Reported-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200928184515.7345-1-krzk@kernel.orgSigned-off-by:
-
Anson Huang authored
Change PINCTRL_IMX to tristate to support loadable module build. And i.MX common pinctrl driver should depend on CONFIG_OF to make sure no build error when i.MX common pinctrl driver is enabled for different architectures without CONFIG_OF. Also add module author, description and license. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1599552721-24872-3-git-send-email-Anson.Huang@nxp.comSigned-off-by:
-
Anson Huang authored
Change PINCTR_IMX_SCU to tristate, add module author, description and license to support building SCU pinctrl core driver as module. Signed-off-by:
-
Anson Huang authored
Use function callbacks for SCU related functions in pinctrl-imx.c in order to support the scenario of PINCTRL_IMX is built in while PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl driver need to initialize the SCU related function callback, and no need to check CONFIG_PINCTRL_IMX_SCU anymore, hence stub functions also can be removed. Signed-off-by:
-
- 27 Sep, 2020 2 commits
-
-
Fabien Parent authored
This commit adds the pinctrl driver for the MediaTek's MT8167 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200907110221.1691168-2-fparent@baylibre.comSigned-off-by:
-
Fabien Parent authored
Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by:
-
- 21 Sep, 2020 2 commits
-
-
Linus Walleij authored
Merge tag 'intel-pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.10-1 * Add last part of cleanup Cherryview driver to align with other drivers * Due to above clean up Cherryview and Baytrail drivers to use common API The following is an automated git shortlog grouped by driver: baytrail: - Switch to use intel_pinctrl_get_soc_data() cherryview: - Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs - Switch to use intel_pinctrl_get_soc_data() - Utilize temporary variable to hold device pointer - Switch to use struct intel_pinctrl - Move custom community members to separate data struct - Drop stale comment intel: - Update header block to reflect direct dependencies - Extract intel_pinctrl_get_soc_data() helper for wider use
-
Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.10 - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1, - Three more conversion of DT bindings to json-schema, - Group all Renesas pinctrl drivers and improve visual Kconfig structure, - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, - Minor fixes and improvements.
-
- 15 Sep, 2020 12 commits
-
-
Geert Uytterhoeven authored
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
-
Geert Uytterhoeven authored
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by:
-
Geert Uytterhoeven authored
The RZ/N1 pin control driver does not use pin groups or pin functions, so there is no need to select GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. Signed-off-by:
-
Geert Uytterhoeven authored
Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Reviewed-by:
-
Geert Uytterhoeven authored
Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by:
-
Geert Uytterhoeven authored
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by:
-
Geert Uytterhoeven authored
For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 42556242 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Acked-by:
Jacopo Mondi <jacopo@jmondi.org> Acked-by:
-
Kuninori Morimoto authored
Sort each driver by description title in alphabetical order. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87h7ssy4qy.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
-
Kuninori Morimoto authored
Now, Renesas Pin Control drivers are under menu, but current descriptions are not aligned. This patch aligns them. - RZ/A2 gpio and pinctrl driver - RZ/N1 pinctrl driver - Emma Mobile EV2 pin control support - R-Mobile APE6 pin control support - R-Mobile A1 pin control support - RZ/G1H pin control support - RZ/G1M pin control support + pin control support for RZ/A2 + pin control support for RZ/N1 + pin control support for Emma Mobile EV2 + pin control support for R-Mobile APE6 + pin control support for R-Mobile A1 + pin control support for RZ/G1H + pin control support for RZ/G1M Signed-off-by: -
Kuninori Morimoto authored
Renesas related pinctrl CONFIGs are located in many places, which is confusing. This patch collects them into the same place, grouped in a new "Renesas pinctrl drivers" menu. This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder. Signed-off-by: -
Kuninori Morimoto authored
It is "Emma Mobile EV2" not "AV2". This patch tidies it up. Reported-by:
-
Geert Uytterhoeven authored
Convert the Renesas Pin Function Controller (PFC) Device Tree binding documentation to json-schema. Document missing properties. Drop deprecated and obsolete #gpio-range-cells property. Update the example to match reality. Drop consumer examples, as they do not belong here. Signed-off-by:
-
- 12 Sep, 2020 3 commits
-
-
Thierry Reding authored
driver_deferred_probe_check_state() may return -ETIMEDOUT instead of -EPROBE_DEFER after all built-in drivers have been probed. This can cause issues for built-in drivers that depend on resources provided by loadable modules. One such case happens on Tegra where I2C controllers are used during early boot to set up the system PMIC, so the I2C driver needs to be a built-in driver. At the same time, some instances of the I2C controller depend on the DPAUX hardware for pinmuxing. Since the DPAUX is handled by the display driver, which is usually not built-in, the pin control states will not become available until after the root filesystem has been mounted and the display driver loaded from it. Fixes: bec6c0ec ("pinctrl: Remove use of driver_deferred_probe_check_state_continue()") Suggested-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200825143348.1358679-1-thierry.reding@gmail.comSigned-off-by:
-
Martin DEVERA authored
I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant DTS part: compatible = "semtech,sx1502q"; gpio4_cfg_pins: gpio2-cfg { pins = "gpio5"; output-high; }; And part of OOPS: [ 0.673996] [<c023cfa6>] (gpiochip_get_data) from [<c023b235>] (sx150x_gpio_direction_output+0xd) [ 0.683259] [<c023b235>] (sx150x_gpio_direction_output) from [<c023b363>] (sx150x_pinconf_set+0x) [ 0.692796] [<c023b363>] (sx150x_pinconf_set) from [<c0238fef>] (pinconf_apply_setting+0x39/0x7e) [ 0.701635] [<c0238fef>] (pinconf_apply_setting) from [<c0236c77>] (pinctrl_commit_state+0xa5/0x) [ 0.710648] [<c0236c77>] (pinctrl_commit_state) from [<c0237e03>] (pinctrl_enable+0xff/0x1d4) [ 0.719139] [<c0237e03>] (pinctrl_enable) from [<c023b791>] (sx150x_probe+0x1a3/0x358) [ 0.727027] [<c023b791>] (sx150x_probe) from [<c02c38bf>] (i2c_device_probe+0x1bb/0x1dc) The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output but gpio is not setup yet. Patch below fixes it but I'm not sure whether is it correct. Link: https://lore.kernel.org/r/f32130bf-cfd4-b1bf-538c-dbc9ee2d947a@eaxlabs.czSigned-off-by:Martin DEVERA <devik@eaxlabs.cz> Signed-off-by:
-
Heiko Stuebner authored
The Rockchip pinctrl driver needs to handle information from Devicetree so only makes sense getting compiled on systems with CONFIG_OF enabled. This also fixes a problem found by the "kernel-test-robot" when compiling the driver on test-builds that do not have CONFIG_OF enabled: drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups': >> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration] 2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | pinconf_generic_dump_config drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register': >> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node' 3473 | gc->of_node = bank->of_node; Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.deSigned-off-by:
-
