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- 05 Aug, 2021 5 commits
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Vinod Koul authored
We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by:
Vinod Koul <vkoul@kernel.org> Tested-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210308060826.3074234-15-vkoul@kernel.orgSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Vinod Koul authored
We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by:
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Vinod Koul authored
We expect bootloader to full memory details but passing empty values can give warning, so add a default value Signed-off-by:
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Martin Botka authored
This commits add support for Sony Xperia 10II based on the SM6125 SoC. Currently working features: - dmesg output to bootloader preconfigured display - USB - eMMC - Volume down button Signed-off-by:
Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210621195308.654587-2-martin.botka@somainline.orgSigned-off-by:
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Martin Botka authored
This commits adds the Device tree file for SM6125 SoC. Signed-off-by:
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- 04 Aug, 2021 35 commits
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Konrad Dybcio authored
Add dma properties to I2C and SPI nodes to make sure DMA transfers can go through. While at it, fix up the property order in SPI nodes to make #address- and #size-cells go after all the meaningful properties. Signed-off-by:
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Bjorn Andersson authored
Shuffle memory regions to make firmware loading succeed and then enable the ipa device. Tested-by:
Steev Klimaszewski <steev@kali.org> Link: https://lore.kernel.org/r/20210615232816.835325-1-bjorn.andersson@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Add DMA properties to I2C hosts to allow for DMA transfers. Signed-off-by:
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Konrad Dybcio authored
This was overlooked earlier, fix it to ensure the busses can work properly. Signed-off-by:
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Konrad Dybcio authored
The autorepeat feature is not needed on gpio-keys. Signed-off-by:
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Konrad Dybcio authored
Enable the internal uSD slot to let the user have more storage. Signed-off-by:
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Konrad Dybcio authored
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Konrad Dybcio authored
Delete the node on Ganges devices, as they use a different one. Signed-off-by:
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Konrad Dybcio authored
After further consideration, it is not worth to keep another separate DTSI, as the differences between Nile and Ganges are very minimal. Instead, let's just address the minimal differences between Kirin and Mermaid. Signed-off-by:
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Konrad Dybcio authored
Let's get loud! Signed-off-by:
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Konrad Dybcio authored
Enable and configure DWC3 and QUSB2 PHY to enable USB functionality on Nile and Ganges boards. Signed-off-by:
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Konrad Dybcio authored
Refer to nodes by their labels to match the current convention. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add all of the RPM PM660/PM660L regulators and the fixed ones, defining the common electrical part of this platform. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Configure the second DSI host/phy and account for them in the mmcc node. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add nodes for camss, cci and its pinctrl in order to bring up camera functionality. Signed-off-by:
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Konrad Dybcio authored
Add IMEM node and PIL reloc info as its child. Signed-off-by:
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Konrad Dybcio authored
This SoC is almost identical to its older brother, SDM660, with a few minor exceptions like the different GPU. Signed-off-by:
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Konrad Dybcio authored
There is SO MUCH common code between these two SoCs that it makes no sense to keep what is essentially a duplicate of 630.dtsi. Instead, it's better to just change the things that differ. Signed-off-by:
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Konrad Dybcio authored
Add VADC, temperature alarm and thermal zones for pm660(l) to allow for temperature and voltage readouts and prevent PMIC overheating. Signed-off-by:
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AngeloGioacchino Del Regno authored
The PM660L PMIC has SPMI regulators on the PMIC SID 3: let's add the compatible in order to probe them. Signed-off-by:
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Konrad Dybcio authored
This will enable backlight control on WLED-enabled devices. Signed-off-by:
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AngeloGioacchino Del Regno authored
The PM660 PMIC has SPMI regulators on the PMIC SID 1: let's declare the second pmic subtree and add the spmi vregs compatible to probe them there. Signed-off-by:
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AngeloGioacchino Del Regno authored
The SDM630 SoC features an Adreno 508.0 GPU with a minimum frequency of 160MHz and a maximum of (depending on the speed-bin) 775MHz. Signed-off-by:
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Konrad Dybcio authored
Enlarge the size to make sure all relevant registers can be reached. This will be required to support the modem. Signed-off-by:
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Konrad Dybcio authored
Configure the ADSP remote processor and add a simple sound{} node to make way for future development. Signed-off-by: -
Konrad Dybcio authored
Add a basic thermal-zones configuration to make sure the SoC doesn't overheat itself to death. Signed-off-by:
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Konrad Dybcio authored
Add SMP2P nodes that are required for ADSP and modem bringup. Signed-off-by:
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Konrad Dybcio authored
This will enable temperature reporting for various SoC components. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
The Adreno SMMU in SDM630 needs this compatible string for proper context handling and split pagetables support. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the required clocks and power domains for the SMMUs to work. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the GPU Clock Controller in SDM630 and keep it disabled by default. Signed-off-by:
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AngeloGioacchino Del Regno authored
The SDHC port 1 has interconnects and can make use of DVFS: define the interconnections and the OPP table in order to optimize performance and power consumption. Signed-off-by:
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AngeloGioacchino Del Regno authored
This will enable usage of (generally) uSD cards. While at it, add accompanying OPP table for DVFS. Signed-off-by:
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AngeloGioacchino Del Regno authored
Previous pinctrl configuration was wrong. Fix it and clean up how multi-pin states are described. Signed-off-by:
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Konrad Dybcio authored
This will let us use USB2 on our devices. The SoC supposedly supports USB3, but there are no known cases of devices that actually have USB3 wired up in hardware. Signed-off-by:
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